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Front-end Design &  Verification Track

Sponsored by:


Moderator: Alex Marin, RnD Team Leader, AMIQ EDA

Oren Katzir

Oren Katzir

VP, Application Engineering & Business Development

Real Intent

11:20 - 11:40

Functional Static Sign-Off’s Expanding Role

System and semiconductor design costs for bug fixing goes up 10X at each design phase. These high costs, plus constantly increasing design complexity have driven the shift left trend in design verification for years, enabling companies to achieve substantial cost reduction and better predict delivery schedules.

This industry-wide shift left has led to the expanded adoption of functional static sign-off tools during early RTL design, including clock domain crossing, reset domain crossing, design initialization, and design for test static sign-off tools.

Oren leads Real Intent’s Application Engineering (AE) team that supports the sales team and customers. He brings to his new position more than 15 years of experience in engineering management, SoC and ASIC design, and development of SoC design tool flows. Previously, Oren was an engineering manager at Intel, leading an SoC engineering team. He also held engineering management positions at Sagantec, Silicon Design Systems, Transchip and Silicon Value. Oren holds a BS in computer engineering from Technion-Israel Institute of Technology.

11:40 - 12:00

Enhance Verification Using Scalable FPGA Prototyping Solution

FPGA prototyping have become key in high speed verification and bug hunting. 
Having a prototyped model running provides high level of confidence in design and verification of the device - this approach also shortens  the time to market by eliminating costly re-spins and providing a platform for early software development. 
The proFPGA product family is a complete and modular multi FPGA solution, which meets highest requirements in the area of FPGA based Prototyping.
The innovative system concept and technologies offer highest flexibility and reusability for several projects, SoC and ASIC prototyping, real time system integration and pre silicon software development.
In this session we will discuss the flow that supports fast bring up of projects on proFPGA platform and also how a scalable and flexible high speed ASIC Prototyping and IP verification solution can be used for early software development and real time system verification.

David has over 20 years of experience in the chip design and EDA industry. His previous experience includes positions at Motorola, Freescale, DSPG, Texas Instruments, Cadence and Mentor Graphics. David holds a  B.Sc and M.EE from the Technion and a MBA from Tel Aviv University.

David Kaushinsky

David Kaushinsky

Senior Application Engineer

Siemens EDA

Alex Marin


Alex Marin

RnD Team Leader


12:00 - 12:20

Hardware Design and Verification IDE built on VS Code or Eclipse: Your Choice

The value of an integrated development environment (IDE) for chip design and verification is well established. Hardware teams save huge amounts of time and resources with such features as on-the-fly code checking, auto-fix suggestions, automatic refactoring, and advanced project navigation and visualization. However, users can be quite picky about the IDE look and feel.

This talk presents two versions of a hardware IDE, one built on the Eclipse platform and the other on the Visual Studio Code (VS Code) platform. Both versions provide similar functionality so that engineers can freely choose between them, but there are some differences in the user experience due to the specific architecture of each platform.

This talk illustrates the major features of an IDE on both platforms highlighting the differences. It discusses how these platforms compare in terms of speed and memory consumption. It concludes with a look at a specific feature in the VS Code version that has proven very popular: the ability to open a secure shell (SSH) connection from the IDE. This enables users to access remote code bases and to spawn compilations on more powerful servers.

With an MSc degree in electrical engineering, Alex started his career as a functional verification engineer. He moved into EDA in 2008 and now is working as an RnD Team Leader at AMIQ EDA.

Nitin Kishore


Nitin Kishore


Truechip Solutions

12:20 - 12:40

Artificial Intelligence Verification-The Future of Chip Verification

Implementation of artificial intelligence (AI) in chip design verification is the futuristic vision of Truechip. The company has already automation and GUI tools which today is capable of automatic test bench generation, automatic environment creation and regression analysis along with performance measurement.

AI coupled with Truechip’s automation tool will revolutionize the design verification. AI will bring more automation in verification. We will have superior testing and verification methods which will use the past data and use AI-ML algorithms to get robust coverage. It will also reduce time-to-market by automation and rapid impact analysis of different implementations.

Coverage and Debugging is also an area which will get gigantic innovations. Stay tuned for our live presentation at SemIsrael to experience Truechip futuristic vision.


Over 22+ years of engineering and management experience, developing and bringing to market over 100 products. Prior to founding Truechip, Nitin was a Design Manager at Freescale Semiconductor (now NXP). Nitin worked at FSL for 10 years. Prior to that Nitin worked at ControlNet, Goa, India. Hands on experience in frontend and backend SoC design flows. Nitin holds a PGDM (Finance) from AIMA, and a BE (Electronics & Telecommunications) from Pune University, India.

Jannik Nielsen.jfif

Jannik Nielsen


Presto Engineering

12:40 - 13:00

The Key Success Factors to Make Your ASIC Project a Game Changer

Key success factors to make your ASIC project a game changer

In this presentation we will focus on key factors making your ASIC project successful.

E.g. ensuring clear objectives enabling a good specification to be defined and to mitigate risk by proving your concept.

Having a well-defined design process and leverage on existing IPs to accelerate development and minimize inherent risk.

Finally – some use cases are presented with examples of completed projects.


Jannik has 20+ years of experience in the semiconductor industry ranging from active designer, team leader and technology management and has been with Presto for 4 years.

Prior to joining Presto, he was with Mellanox Technologies for 5 years working on ASICs for high-speed optical communication and before that he was 7 years with Analog Devices working on digital audio solutions.

He holds a M.Sc.E.E. degree and a Ph.D. degree from the Technical University of Denmark where he was assistant professor before joining industry.

13:00 - 14:00 : Lunch, Exhibit Viewing

Oren Katzir
David Kaushinsky
Alex Marin
Nitin Kishore
Jannik Nielsen
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