Architecture, IP & SoC Design
11:40 - 13:00
Track Moderator
Bio
11:40 - 12:00
Gil Golov, M. Sc.
Senior Director Solution, SoC Marketing
Socionext Europe GmbH, Langen
Automotive-Grade Chiplets: Reliability, Safety, and Design Challenges
Chiplet-based SoC design offers a scalable solution for ADAS and autonomous driving, overcoming monolithic SoC limitations in cost, performance and flexibility. Modular architectures enable heterogeneous integration of multiple SoC and HBM DRAM dies, delivering hundreds of teraflops required for L4/L5 autonomy. Key challenges include high-bandwidth interconnects, power delivery, thermal management, advanced packaging and automotive-grade reliability. Through real-world examples, the session explores advanced design and verification methodologies, highlighting how UCIe standards and ecosystem collaboration enable scalable, high-performance automotive computing platforms.
Bio
Gil Golov is a seasoned semiconductor executive with over 20 years of experience in SoC design, chip architecture, and business development. He currently serves as Senior Director Solution SoC Marketing at Socionext, where he collaborates closely with customers to develop custom SoC solutions for various application areas, including Automotive. Previously, Gil held senior leadership positions at Synopsys and Micron, where he led international design, architecture and technical marketing teams. He began his career as an ASIC design engineer and holds over 60 patents related to Semiconductors and Automotive applications.
12:00 - 12:20
Moshe Stolar
Senior Staff CAE
Arteris
What Functional Tests Can't See: Tracking Asset Movement on the SoC
Functional testing is very good at showing that a design does what it should. Asset movement is a different question: where a protected value, an asset, went along the way, such as a key, a lock bit, firmware, or tenant data moving from the block that produces it to the block that uses it. Copies can end up in buffers and interconnect logic that are often outside what a test was written to cover. This session walks through examples of what is hard to observe with functional testing alone, and how Information Flow Tracking (IFT) makes asset movement observable, which matters at the system-on-chip (SoC) level. As security assurance moves beyond "does it work" toward "where did the asset go," attendees will leave with new questions to ask of their designs.
Bio
12:20 - 12:40
Wim Van Seters
European Sales
SiFive
The RISC-V Revolution: How SiFive Is Scaling RISC-V Architecture Everywhere
Invented in 2010 at UC Berkeley by the co-founders of SiFive, RISC-V is rapidly expanding across every major computing segment. Join this introductory 101 session to explore the growth of RISC-V and discover how SiFive’s portfolio of processor IP meets customer needs across a diverse range of applications.
Bio
Semiconductor industry professional with extensive experience in intellectual property (IP), processor technologies, and international business development. Passionate about RISC-V, AI, custom silicon solutions, and bringing innovative technologies to customers in the EMEA region.
12:40 - 13:00
Nitin Kishore
CEO
Truechip
NoC for Chiplets and AI SoCs
As AI workloads explode and the industry shifts toward multi-die architectures, the ultimate bottleneck is no longer compute it is communication. Moving massive volumes of data efficiently between processors, accelerators, and memory dictates the success of modern silicon. This presentation explores how advanced Network-on-Chip (NoC) architectures act as the intelligent central nervous system for next-generation AI SoCs. We will unpack how modern NoCs deliver scalable connectivity, route traffic with ultra-low latency, and unlock the true potential of chiplet ecosystems. Attendees will gain deep insights into critical design vectors, including Quality of Service (QoS), dynamic traffic prioritization, and seamless die-to-die integration.