Expert presentations, various topics, live Q&A
SemIsrael Tech Webinar
January 21, 2025
14:00 - 17:00
(Israel Time Zone)
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Webinar Agenda
Lee Harrison
Tessent Product Marketing Director
Siemens EDA
14:00 - 14:30
DFT, SLM, In-system test
In-System Test, A Critical element to SLM
Continuous testing and monitoring of devices is required to guarantee optimal performance, reliability and safety throughout their operation. Tessent In-System Test enables the application of high-quality deterministic test patterns as part of an SLM Implementation
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BIO:
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 20 years of industry experience with Siemens Tessent DFT products and has been involved in the specification of new test features and methodologies for Siemens customers. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, ATS, DATE etc.
Yaacov Belenky
Chief Innovation Officer
FortifyIQ
14:30 - 15:00
Secure SoCs, Regulatory Compliance, Hardware Security, Side channel, DPA, SCA
Semiconductor Security Simplified: Efficient, Simple, Scalable Solutions for SoCs and IoT
What If Security Could Boost Performance?
What if protecting your devices didn’t come at a cost—but instead enhanced performance, reduced power consumption, and saved silicon area?
In this webinar, we’ll unveil groundbreaking security solutions that redefine expectations, offering protection so seamless that even unregulated industries can benefit. Whether you’re designing for IoT, smart cards, medical devices, or next-gen SoCs, our solutions open doors to efficiency, compliance, and innovation—all in one package.
Curious about how security can transform your designs? Join us to find out.
Key Takeaway: Discover a new paradigm in device security—protection that performs.​
BIO:
Yaacov, a mathematician, has 26 years of extensive experience in semiconductor security. He has written 7 academic papers and has 40+ patents in the semiconductor security domain. He’s held key security positions at NDS, Intel, Cisco and now at FortifyIQ.
Jayant D‘Souza
Technical Product Director
Siemens EDA
15:00 - 15:30
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Scan Test, Scan Diagnosis, Chain Diagnosis, Clock Tree Defects, Transistor Defects, Yield Analysis, Fault Isolation
Hi-Res Chain Diagnosis
Chain diagnosis is a powerful tool to localize manufacturing defects that cause scan chain shifting to fail. In this talk, we will explore 3 new technologies that further advance the localization of chain defects.
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BIO:
Jayant D’Souza is the technical product director for yield learning products in the Siemens EDA Tessent® group. Jayant holds an MSEE degree from the University of North Carolina at Charlotte (USA). He has about 20 years of experience in the design-for-test (DFT), automatic test pattern generation (ATPG), scan diagnosis and yield learning areas. He is currently focused on the application of DFT and scan on defect diagnosis and yield learning.
Elad Alon
CEO and co-founder
Blue Cheetah Analog Design
15:30 - 16:00
Chiplets, Interconnect, die-to-die, PHY, IP, UCIe, BoW
Emerging Chiplet Ecosystems Enable Innovative Multi-Vendor Designs
Chiplets reduce the rising costs of innovation. Heterogeneous compute, especially AI applications, stands to gain the most from chiplet-based designs. System architects are discovering that the keys to successful chiplet integration are an application-appropriate ecosystem and a customizable die-to-die (D2D) interconnect tailored for their end applications.
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BIO:
In addition to his role as CEO and co-founder at Blue Cheetah, Elad’s experience includes Adjunct Professor at UC Berkeley, co-director of the Berkeley Wireless Research Center, and consulting positions with numerous global semiconductor companies. He received his Ph.D., M.S., and B.S. degrees from Stanford University, and is an IEEE Fellow.
Juergen Jaeger
Director of Prototyping Product Strategy
Siemens EDA
16:00 - 16:30
FPGA-based Prototyping, HW/SW Verification, Software Validation
Veloce proFPGA CS – FPGA-based Prototyping with AMD VersalVP1902 Enables New Use Modes
With the AMD VersalVP1902 FPGA device, delivering double the capacity of previous FPGAs, you unlock a whole new level of performance and cost-effectiveness. In this webinar, hear how Siemens’ Veloce proFPGA CS prototyping platform can improve your FPGA prototyping efficiency, productivity and expand use modes.
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Map more of your design onto a single chip
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Run faster than ever before
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Reduce the cost per gate by 50% or more
Learn how to map and debug much larger designs into the multi-FPGA Veloce proFPGA CS platform by taking advantage of the powerful VPS (Veloce Prototyping Software) tool suite.
Who Should Attend
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Verification engineers and managers
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Prototyping engineers
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Embedded software development engineers
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System architects and verification engineers
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HW/SW integration engineers
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BIO:
Juergen Jaeger is the director of prototyping product strategy for Siemens EDA. Prior to joining Siemens EDA, Juergen was director of product management at Cadence Design Systems, responsible for all FPGA-based prototyping activities. Prior to that he worked at Synopsys via the acquisition of Synplicity where he was the marketing director for prototyping products. Before Synplicity he was product marketing manager for the IKOS V-Station hardware emulation systems for several generations including product launches. Juergen has a master’s degree in electrical engineering from the technical college in Kaiserslautern, Germany. Juergen spent the first part of his career in engineering and application engineering in Germany.