Product Marketing Manager, Scalable Verification Solutions Division
11:00 - 11:30 I ASIC Verification
Veloce proFPGA: The Perfect Complement for Your System Verification Flow
The Veloce proFPGA prototyping platform has been explicitly designed as a complement to the Veloce Strato and Primo platforms. That means that a hardware design can be conveniently compiled for any of the Veloce systems with minimal effort. In addition to making the development process more efficient, it also means that prototyping – and therefore software design – can start earlier, since hardware changes can be easily and smoothly ported to the prototype as the design matures. Find out how the Veloce proFPGA platform brings value to your software and hardware/software verification flow.
Gabriele Pulini is a Product Marketing Manager in the Scalable Verification Solutions Division at Siemens EDA. He has more than 20 years of EDA experience, with 14 years specializing in hardware emulation.
Snr Director, Product Management
11:30 - 12:00 I Emulation Queuing
Emulation - Getting a Better Return on Your Investment
Existing techniques for Emulator usage optimization focus on job packing and gate utilization. While these are useful metrics, they are incomplete. In this presentation we will show a new product, Hero, that allows for sharing of emulation across multiple teams and optimizes total simulation cycles while maintaining good turn-around-times for both Simulation Acceleration and In-Circuit Emulation/Interactive tasks.
Stuart Taylor manages computer infrastructure products used by many chip design teams world-wide. He joined Altair Engineering from the Runtime DA acquisition in 2017. He has worked on CPU, GPU and system ASICs for ATI, AMD, Intel and Sun Microsystems. He started his career at Fairchild Semiconductor.
12:00 - 12:30 I DFT For Automotive
Design-For-Test Design (DFT) Consideration for Automotive Designs
These days we hear DFT concepts for automotive devices being regularly discussed within the industry. However, this was not always the case. DFT was previously thought of as an afterthought or mundane task. Now, with the advancement of automotive design, DFT can be appreciated for what it is. A chip design facet that is evolving, with innovation and interesting challenges that arise alongside.
The scope of this paper is on DFT consideration for executing automotive projects. Traditionally, DFT engineers have always pushed for DFT considerations to start at project conception. With automotive this requirement has pushed even further upstream to system level. DFT as we know, is about manufacturing defects, and shipping products with extremely low Defective Parts Per Million (DPPM). Automotive brings additional requirements of safety and reliability which involves In-System Test (IST). Careful consideration of aspects of DFT methodologies are needed to maintain high coverage, aiming for low DPPM, and still allowing for the ability for In-System Test that meets ISO26262 safety standard.
In this paper, we further explore how DFT plays an integral part of chip design execution and why careful consideration must be taken when undertaking automotive projects.
Ijeoma has over 25 years VLSI experience with expertise in Design for Test. She has developed automotive LBIST implementation flow. Technically led tape-out at TSMC 16nm FFC. She has led DFT team from architectural specification to production.
Previously worked at Philips/NXP, Intel.
Ijeoma holds an MSc in Microelectronics System Design and PHD in Digital Test from Brunel University, London.
DFT Team Lead
Field Application Engineer Israel & Europe
12:30 - 13:00 I Low-power Vector AI Processing
Introducing SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA
While we are only scratching the surface of the incredible impact AI/ML is having on organizations as they adopt these functions in their daily business, it’s evident that the workloads, algorithms, and requirements are constantly evolving. SiFive delivers adaptable AI/ML solutions, based on the RISC-V vector ISA, with a flexible, future-proof approach enabled by efficient, programmable building blocks of hardware IP. This talk will detail the innovative capabilities of the Linux-capable SiFive Intelligence X280 and SiFive Performance P270 processors which enable customers to develop programmable, scalable, and configurable platforms to meet modern AI/ML processing requirements from the edge to the cloud.
I'm SiFive Field Application Engineer in the configurable processors domain specializing in embedded software.
I've worked in several semiconductor companies where I was responsible for the firmware design, implementation, and bring up.
The last couple of years I've been working in a customer-facing role, bringing customer requirements into processor-based SoC implementations.
Currently, I work closely with a wide range of customers adopting the emerging RISC-V Architecture.
13:00 - 15:00 I Break
Product Engineer, Design for Test
15:00 - 15:30
Tessent Streaming Scan Network (SSN): No-compromise DFT
The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT is no longer enough. Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between DFT implementation effort and manufacturing test cost by decoupling core-level and chip-level DFT. With SSN, a true no-compromise approach to DFT is possible.
Peter who has been working for Siemens since 2018 is a member of the Tessent DFT technical marketing team. Pete’s primary focus during his time at Siemens has been the development and successful deployment of Streaming Scan Network (SSN) product. As the customer facing technical lead for the SSN product, Pete has been teaching and providing guidance to internal colleagues and external customers on how to implement SSN. Pete’s role in SSN continues to expand with the development and deployment of new features being added to SSN regularly.
Prior to joining Siemens, Pete has worked in the silicon industry for 25 years, with most of that time in the field of DFT, for such companies as Marvell Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.
Vice President Sales,
15:30 - 16:00 I RISC-V Software Development
Why Wait For Hardware to Start RISC-V Software Development?
The rapid adoption of the open standard RISC-V instruction set architecture (ISA) has focused on the ISA specification and various implementations. The software ecosystem has been an afterthought. This is understandable because the RISC-V ISA is a hardware standard, however, it neglects the fact that software is often the critical path to SoC adoption.
Virtual platforms, or software simulation, are one tool that can accelerate software development. While instruction accurate virtual platforms have been available for more than 15 years, use of virtual platforms has become mainstream methodology over the last 5 years. Virtual platforms provide better controllability, observability, repeatability and ease of automation versus other prototyping and development tools, and can be deployed very early in the project. Virtual platforms are particularly helpful for hardware dependent software – software that runs directly on the processor. This includes operating systems, drivers, firmware and importantly AI/ML compilers.
This talk will highlight the use of virtual platforms for RISC-V software development, providing examples not only of software development but also of the use of virtual platforms to provide key insights on the design tradeoffs which can be further optimized with custom instructions.
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in
addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
Director of Applications Engineering (North America)
16:00 - 16:30 I Design & Verification IP
Making MIPI Your Ally
If you’re looking at a screen, there’s a good chance that MIPI is involved. Though this processor interface continues to be in routine use for smartphones and other mobile technology, MIPI has transcended traditional camera and display applications. It’s on our wrists in wearables. It has made its way into our cars in the form of Advanced Driver Assistance Systems (ADAS) and infotainment systems. IoT has brought it into our homes.
Focusing on SmartDV’s MIPI SPMI Verification IP and MIPI Debug Design IP as examples, Bipul Talukdar offers context for the many potential applications of MIPI and the opportunities it affords chip designers. Topics covered include:
Overview of MIPI specification and technology
Must-haves for PHY selection and integration
Pointers on successfully integrating MIPI IP into your designs
Join us to learn how you can make MIPI your ally!
Bipul Talukdar is Director of Applications Engineering for SmartDV North America. He is an expert in hardware functional verification with a specialty in verification IP (VIP) development, formal property verification, and hardware emulation. He leads application engineering and support for SmartDV’s verification and design IP library of over 800 products.
Bipul has a strong background in formal verification of RISC-V based cores/subsystems and coverage-based closure. His previous engineering roles at SiFive, Cadence, and Mentor Graphics (Siemens) give him a broad perspective on the myriad challenges faced by design and verification teams, allowing him to partner with customers for success throughout product evaluations and deployment.
Since joining the team at SmartDV in 2019, Bipul has taken an active role in the company’s business development. He has distinguished himself as a technical thought leader, routinely publishing articles and representing SmartDV as a speaker at semiconductor industry conferences.
Bipul holds a Bachelor of Science in Engineering, Electronics, and Telecommunication from India’s National Institute of Technology, Silchar. He is based in San Jose, California.
16:30 - 17:00 I Physical Planning and Timing Closure
Excellicon Product Portfolio
Timing Constraints and Physical Planning Platform – Excellicon focus is on helping designer from early stages to ensure timing constraints are properly developed and verified prior to handoff to physical design implementation. Product portfolio is designed to ensure quickest and most efficient path to timing closure and reducing unnecessary iterations. Our products facilitate automatic generation of timing constraints including constraints promotion, demotion, budgeting, verification, equivalence checking etc. On the physical side, the products provide capabilities to perform early floorplan verification, Clock tree analysis, floorplanning and RTL restructuring.
Over 20 years of chip design experience, designing complex SOCs in networking, communications, imaging, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon, Himanshu served as an advisory board member of several EDA companies. His experience is crucial to ensuring development of tools fit for everyday design by front and back-end engineers and shaping the future direction of Excellicon