Expert presentations, various topics, live Q&A

SemIsrael Tech Webinar

September 13, 2022
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September 13, 2022
11:00 - 17:00

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Sergio Marchese

Senior Member of Technical Staff


11:00 - 11:30 I USB4 - Development of Host/Device

USB4 – Promises and Challenges

The USB4 specification was released in 2019. It’s promise was to bring a new level of convenience to the end user. One cable to power all devices, connect them, and make optimal use of the available bandwidth. And more speed, of course! Think about instantly transmitting large amounts of data while simultaneously driving a high-resolution display, for example. As the industry moves towards widespread adoption of USB4, there is a pressing need for trustworthy, specification-compliant, and mature USB4 IPs. This presentation starts with a brief history of the USB standard, continues examining some of the innovative aspects of USB4, and outlines a few key challenges facing hardware development teams developing USB4 IPs.


Sergio Marchese is Senior Member of Technical Staff at SmartDV Technologies. He has 22 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high- integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.

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Lee Harrison


Automotive IC Solutions Manager

Siemens EDA

11:30 - 12:00 I Functional Safety

Meeting the Challenges of ISO26262 Using Tessent In-System Test and In-life Solutions

A growing proportion of the modern-day automotive electronics are there to support new advanced driver-assistance systems (ADAS). The demands of safety-critical ADAS systems introduce new challenges to semiconductor designers in meeting functional safety requirements defined by the ISO 26262 standard. This webinar will talk about how In-System DFT technologies can be leveraged to meet the ISO 26262 functional safety requirements and how they can support modern In-Life automotive requirements.


Lee Harrison is Automotive IC Solutions Manager, at Siemens EDA.  He has over 20 years of industry experience with Siemens Tessent test, safety and security products, with a focus on automotive, Lee is working to ensure that current and future test, safety, security and analytics requirements of Siemens’s automotive customers are understood and met. Lee received his BEng in MicroElectronic Engineering from Brunel University London in 1996

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Shreyas Derashri

Vice President of Compute

Imagination Technologies

12:00 - 12:30 I Heterogeneous Compute

New Era of Compute

On one hand, the laws of compute (Moore’s law, Dennard Scaling, Amdahl’s law) are slowing down or have already come to an end, but on the other hand, the compute needs of the industry are growing at an exponential rate. This webinar asserts that the future is around efficient heterogeneous compute. Further this webinar talks about how Imagination with its RISC-V CPUs, GPUs and AI IP is providing the building blocks for this future.


Shreyas is currently Vice President of Compute at Imagination, responsible for Imagination’s CPU, AI and Heterogeneous compute products and solutions.  

He has spent 20 years in the technology industry both in start-ups and in large corporations in various roles. He started his journey in the UK designing CPUs at Arm before moving to a start-up, Apical, where he was a core catalyst in its successful journey from an early start up stage through to acquisition. At Apical his roles included Head of Engineering and Head of Strategic Marketing. Apical was acquired by Arm for $350m and its technology has found its way into 2billion+ devices. After spending a further few years at Arm looking after product management, he joined Imagination in 2019 to work on business development and then moved into a product leadership and strategy role.

Shreyas holds an MBA from Cambridge Judge Business School, Masters in Analogue and Digital IC Design from Imperial College London, graduating top of his class with distinction. Shreyas is also the recipient of Bhamashah award (India) with double gold medal for his B.Eng. in Electronics and Communications.

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Gabriele Pulini

Product Marketing Manager, Scalable Verification Solutions Division

Siemens EDA

12:30 - 13:00 I SoC Verification and Validation

Veloce proFPGA Enables Early FW/SW Development and High System Flexibility

This webinar explains how adding the Veloce proFPGA prototyping platform has been explicitly designed as a complement to the Veloce emulation and enterprise prototyping platforms. That means that a hardware design can be conveniently compiled for any of the Veloce systems with minimal effort. In addition to making the FW/SW development process more efficient, it also means that prototyping – and therefore software design – can start earlier, since hardware changes can be easily and smoothly ported to the prototype as the design matures. Find out how the Veloce proFPGA platform brings value to your software and hardware/software verification flow. Attend this webinar to learn how the Veloce proFPGA platform enables early FW/SW development, high debug productivity and high system flexibility.


Gabriele Pulini is a Product Marketing Manager in the Scalable Verification Solutions Division at Siemens EDA. He has more than 20 years of EDA experience, with 14 years specializing in hardware emulation.

13:00 - 14:30 I Break

Brian Walsh

Director of Sales


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14:30 - 15:00 I Cybersecurity

Ensuring “Security by Design” with a Systematic Approach

Security vulnerabilities may be introduced during implementation of SoC hardware at the block or subsystem level, or during system integration when the full SoC is configured with system firmware and software. The goals of a secure architecture are not met if it is misused or misconfigured during RTL development or firmware configuration, however current approaches either do not or cannot detect the presence of misconfiguration, or the consequences. Independent block, subsystem, or software testing leaves gaps in security validation and cannot always ensure that security requirements are met. 

This presentation will discuss the growing importance of analyzing security vulnerabilities pre-silicon and how to leverage rigorous methodology combined with technology to provide increased security assurance to achieve pre-silicon security signoff.


Brian Walsh is Director of Sales at Cycuity, currently focused on managing the Military and Aerospace sectors. Brian has over 20 years of experience in Electronic Design Automation, having worked previously at Synopsys, Atrenta and most recently Siemens, where he was responsible for their Analog Mixed Signal business (Tanner) in the Central and Eastern Regions of North America. He joined Cycuity in early 2020 to continuing growing sales in same geographies, while also helping the company expand into Europe.  Brian received his B.S. in Electrical Engineering from the University of Maine.​

Salvador Alvarez

Senior Manager of Product Planning


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15:00 - 15:30 I AI/ML

Unlocking the Full Potential of FPGAs for Real-Time ML Inference – Tuning an Overlay to an Architecture

An FPGA can be a very attractive platform for many Machine Learning (ML) inference requirements. It requires a performant overlay to transform the FPGA from a generic solution into a highly capable AI inference accelerator. In this presentation, using the example of automatic speech recognition (ASR), we will explore how an overlay can be used to optimally leverage the potential performance of an FPGA architecture. We review the key components required in the FPGA architecture, such as a 2D Network on Chip (NoC), high speed external memory and optimized Ma​chine Learning Processor (MLP), and how the choice of numerical precision can affect performance and ease of use. Using standard benchmarks, we demonstrate an ASR appliance that can reduce costs by as much as 90% compared with alternative approaches.


Salvador Alvarez is the Senior Manager of Product Planning at Achronix, coordinating the research, development, and launch of new Achronix products and solutions. With over 20 years of experience in product growth, roadmap development, and competitive intelligence and analysis in the semiconductor, automotive, and edge AI industries, Sal Alvarez is a recognized expert in helping customers realize the advantages of edge AI and deep learning technology over legacy cloud AI approaches. Sal holds a B.S. in computer science and electrical engineering from the Massachusetts Institute of Technology.

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David Bouse

Principal Technology Leader


15:30 - 16:00 I PCI Express 6.0

PCI Express 6.0 – Physical Layer Characterization of a Low Latency PAM4 Link at 64GT/s

David Bouse, Principal Technology Lead from Tektronix, will provide an update on PCI Express 6.0 with an emphasis on Physical Layer design and characterization at 64 GT/s PAM4. The emergence of new data center applications requiring AI/ML, high-performance computing, and increasing Networking bandwidths are some of the drivers of this latest inflection point. New protocols such as CXL leverage the PCIe protocol layer and enable cache coherency for increasing memory demands. The legacy CEM form factor has managed to maintain backward compatibility propped up by PCB layout optimizations and we’ve seen the emergence of numerous form factors including M.2 and EDSFF “Ruler” reach high volume manufacturing with fewer interoperability standardizations. David’s talk will bring clarity to this healthy yet complex ecosystem with a deep dive into the latest methodology for characterizing transceivers at 64 GT/s supporting different protocols across the numerous form factors expected in the years to come.


David Bouse is a Principal Technology Leader at Tektronix with expertise in highspeed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture. David represents Tektronix within the PCI-SIG and CXL standard bodies contributing to the Electrical and Serial Enabling groups participating in the Base, CEM, and test specification development. Pathfinding is his specialty for stressed eye calibration techniques and transmitter characterization to advance data rate speed. David leads numerous gold test suites at the PCI-SIG compliance workshops and helps to develop future programs with an emphasis on test and measurement correlation. David supports real time oscilloscope and receiver hardware test development and is the technical leader for the Tektronix PCI Express and CXL solutions. He authored the PCI Express 4.0 Physical Layer test specification while previously at Intel, designed PCIe/USB test fixtures, and was the lead software developer for the SigTest compliance and validation tool.

Larry Lapides

Vice President Sales

Imperas Software

16:00 - 16:30 I RISC-V Verification

Advanced RISC-V Processor Verification and Methodologies

The open standard RISC-V Instruction Set Architecture (ISA) is driving a new wave of innovation through the SoC and hardware design teams. With RISC-V it is possible to build an optimized processor with just the right mix of features and functions, using standard extensions and custom instructions that leverage the growing ecosystem of software and tools. RISC-V provides developers new design freedoms and flexibility, but with these innovations the challenge will be to achieve time-to-market with a fully verified, production ready RISC-V implementation.

This talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications, including the innovations in processor designs with features such as: out-of-order pipelines, hardware multi-threading, multi-hart, custom extensions and advanced privileged modes, plus vector accelerators.
Key updates will focus on functional coverage, Verification IP (VIP) and testbenches for asynchronous events, with examples from customers, partners and users at the forefront of RISC-V adoption.


Prior to joining Imperas, Larry ran sales at Averant and Calypto Design
Systems. He was vice president of worldwide sales during the run-up to
Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity
solidified its position as the fifth largest EDA company. Before Verisity
and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.

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Stephane Cordova


Intento Design

16:30 - 17:00 I Analog Design

How to Speed-up Your Analog IC Design Flow With ID-Xplore?

A typical design flow requires going through “manual” tasks with lots of time-consuming iterations. This empiric approach results in days of work before getting a correctly sized schematic. Intento Design ID-Xplore tool uses graph-based disruptive innovation to provide fast design space exploration in any technology and propose fast design migration over any technologies to answer the current challenge of the semiconductor industry to increase capacity and lower cost.

Stephane Cordova is CEO of Intento Design. He has 30 years of experience in semiconductors, and business development of analog, digital and software solutions in Europe, North America, and Japan. His expertise covers analog and mixed signal IC, high performance processors, including associated software solutions serving a wide range of applications such as automotive, telecom and artificial intelligence.