Front-End Design & Verification
11:40 - 13:00
Track Moderator
Bio
11:40 - 12:00
Oren Katzir
Vice President Application Engineering
Real Intent
Transforming Static Sign-off in SoC Design Through Microarchitectural Analysis and AI Integration
This presentation outlines Real Intent’s strategy to transform static sign-off applications for IC design, enabling earlier functional verification (“shift left”).
The first pillar, Microarchitecture Analysis (MA), automatically identifies Standard Functional Components (SFCs), including FSMs, FIFOs, RAMs, and counters, from complex RTL. It powers Conquest MAI for structural integrity checking and Meridian MA-CDC, delivering 98% error identification precision while reducing designer review effort by 95%.
The second pillar introduces Riven Sign-Off AI Agent, integrating agentic AI with MCP and VSCode to simplify debugging and database interaction through natural language. Together, these innovations reduce sign-off noise, strengthen structural integrity, and accelerate functional verification.
Bio
Oren leads Real Intent’s Application Engineering (AE) team @ Real Intent. He brings to this position more than 20 years of experience in engineering management, SoC and ASIC design, and development of SoC design tool flows. Previously, Oren was an engineering manager at Intel, leading an SoC engineering team. He also held engineering management positions at Sagantec, Silicon Design Systems, Transchip and Silicon Value. Oren holds a BSEE in computer engineering from Technion-Israel Institute of Technology.
12:00 - 12:20
Yael Abarbanel
Distinguished Engineer - Agentic AI
Cadence Design Systems
ChipStack AI Super Agent for RTL Design and Verification
Bio
Yael Abarbanel brings 34 years of technology leadership in the Software and CAD industry, having held leadership positions at IBM (8 years) and Intel (25 years) and currently at Cadence (1.5 years). She initiated and led the development key technologies and methodologies for verification across pre-silicon, post-silicon, hardware, and firmware domains. At Cadence, she is part of the central Agentic AI Group, supporting collaborative efforts to advance AI technologies that enable autonomous chip design.
12:20 - 12:40
TBD by Siemens EDA
Bio
12:40 - 13:00
Oren Gabay
Chief Executive Officer
OpenLM
Your Compute Became Elastic. Your Licenses Didn't.
Overnight regressions come back empty and the post-mortem blames the farm. Often, the real issue is licensing. Xcelium couldn't get parallel tokens, VCS aborted on a missing feature, or Questa hit the peak-user limit, while licenses were likely sitting idle elsewhere in the organization.
Over the past decade, compute capacity became elastic: more cores, schedulers, and cloud bursting on demand. License pools remained fixed, tied to servers and managed independently of compute schedulers. LSF, Accelerator, and Slurm schedule cores, while license managers issue tokens. Neither has visibility into the other.
This session examines where EDA licenses are consumed—from batch farms and workstations to cloud bursts, global teams, and abandoned interactive sessions—and how poor allocation impacts schedules rather than budgets. The core argument is that license challenges stem from visibility and allocation, not scarcity, and can be addressed through license-aware infrastructure connecting schedulers and license managers.