Agenda
November 29, 2022
SemIsrael Expo 2022 is packed with professional content; great keynote speakers, and 4 professional tracks:
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IP & Cores
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Front-end Design & Verification
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Physical Design
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Post Silicon
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Professional tracks presentations will start after a general assembly session.
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Event agenda - General
08:00 - 09:15
Breakfast, Exhibit Viewing
09:15 - 10:30
10:30 - 11:20
Break, Exhibition Visit
11:20 - 13:00
Professional Tracks - Part 1 (IP & Cores, Front-end Design & Verification, Physical Design)
13:00 - 14:00
Lunch, Exhibit Viewing
14:00 - 15:40
Professional Tracks - Part 2 (IP & Cores, Post Silicon)
15:40
Summary, Lucky Draws
Keynote Speakers (General Assembly)
(click here for detailed general assembly agenda)
09:15 - 09:30
Welcome Notes
Shuka Zernovizky
Founder, SemIsrael
09:30 - 09:50
Digitalization Verification and Validation – Challenges and Directions
VP and GM , HW Assisted Verification, Siemens EDA
09:50 - 10:10
Driving the Photonic IC (R)evolution
Director of Product Management & Marketing, Synopsys
10:10 - 10:30
The Impact of AI in Intelligent System Design
Matt Graham
Product Engineering Group Director, System and Verification Group, Cadence
IP & Cores Track
(click here for detailed track agenda)
Moderators:
Shin (Shimon) Raviv, Director Product Marketing, Weebit Nano
​Ilan Sever, VP R&D, Weebit Nano
11:20 - 11:40
Expanding DFT Automation for 2.5D / 3D IC
Technical Account Manager, IC Verification & Validation, Siemens EDA
11:40 - 12:00
A Trusted Partner to Watch Your Back and Pave Your Path to Success
Sr. Director Sales, Alphawave IP
12:00 - 12:20
Enabling Software Developers with Software Acceleration with Reconfigurable Hardware Functions
Andy Jaros
VP Sales and Solutions Architecture, Flex Logix Technologies
12:20 - 12:40
SiFive Automotive, Transforming Safety-critical Applications With RISC-V Processors
Field Application Engineer, SiFive
12:40 - 13:00
13:00 - 14:00
Lunch, Exhibit Viewing
14:00 - 14:20
A Scalable Framework for Fast Design Space Exploration of AI Workloads in [Complex] SoCs
Head of Solution Architectures, Sondrel
14:20 - 14:40
Actionable Insights Through Silicon Lifecycle Monitoring and Analytics
Avi Braun
Business Development Manager, Hardware Analytics & Test for Europe, Synopsys
14:40 - 15:00
Agile Analog’s Approach to IP Design, Quality - Why “Silicon Proven” is Not What You Think
Co-Founder and Strategy Consultant, Agile Analog
15:00 - 15:20
Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
Patrick Verbist
Product Marketing Manager, ASIP Tools, Synopsys
15:20 - 15:40
Multi-Die Systems – Challenges and Solutions
Sr. Manager, Applications Engineering DesignWare IPs, Synopsys
Front-end Design & Verification Track
(click here for detailed track agenda)
Sponsored by:
Moderator: Alex Marin, RnD Team Leader, AMIQ EDA
11:20 - 11:40
Functional Static Sign-Off’s Expanding Role
VP, Application Engineering & Business Development, Real Intent
11:40 - 12:00
Enhance Verification Using Scalable FPGA Prototyping Solution
Senior Application Engineer, Siemens EDA
12:00 - 12:20
Hardware Design and Verification IDE built on VS Code or Eclipse: Your Choice
RnD Team Leader, AMIQ EDA
12:20 - 12:40
Artificial Intelligence Verification-The Future of Chip Verification
CEO, Truechip Solutions
12:40 - 13:00
The Key Success Factors to Make Your ASIC Project a Game Changer
Jannik Nielsen
VP R&D, Presto Engineering
13:00 - 14:00
Lunch, Exhibit Viewing
Physical Design Track
(click here for detailed track agenda)
Sponsored by:
Moderator: Nahum Rozen, Aprisa P&R Application Engineering Specialist, Siemens EDA
11:20 - 11:40
Multi-die System Design and 3D, The Next Big Step in IC Evolution
Leon Rabinovich
Senior AE, Synopsys
11:40 - 12:00
Under the Hood of OpenFPGA
Pierre-Emmanuel Gaillardon
CTO, Rapid Silicon
12:00 - 12:20
New Layout Methodologies and ​Advanced Node Automation
Yonatan Kliger
Application Engineer Director, Cadence
12:20 - 12:40
Intrinsic Intelligent P&R For Advanced Node Designs
Aprisa P&R Application Engineering Specialist, Siemens EDA
12:40 - 13:00
Power (Source) Aware Floor Planning
Jorge Antonio Araiza Martinez
Technical Layout Lead, ICMASK
13:00 - 14:00
Lunch, Exhibit Viewing
Post Silicon Track
(click here for detailed track agenda)
Sponsored by:
Moderator: Ronen Livni, ATE Test and Product Manager, Vayyar
14:00 - 14:20
Why Advanced Packaging & 3D Integration Does Matter to Everybody
Founder & CEO, Monozukuri
14:20 - 14:40
30 Thousand Wafers in Your Browser
John O'Donnell
Founder and CEO, yieldHUB
14:40 - 15:00
15:00 - 15:40
Advanced Packaging & Challenges for Test
Vice President, Global Test Services, Amkor Technology