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October 24, 2023

SemIsrael Expo 2023 is packed with professional content; great keynote speakers, and 4 professional tracks:

  • IP & Cores

  • Front-end Design & Verification

  • Physical Design

  • Post Silicon

Professional tracks presentations will start after a general assembly session.


Event agenda - General

08:00 - 09:00

Breakfast, Exhibition Visit

11:00 - 11:40

Break, Exhibition Visit

11:40 - 13:20

13:20 - 14:20

Lunch, Exhibition Visit

14:20 - 15:40


Summary, Lucky Draws

Keynote Speakers (General Assembly)
(click here for detailed general assembly agenda)


09:00 - 09:20

Welcome Notes

Shuka Zernovizky

Founder, SemIsrael

09:20 - 09:40

AI Disruption of Intelligent System Design

Vivek Mishra

Corporate Vice President, Product Engineering, Cadence

09:40 - 10:00

Extending RISC-V Intelligence from Cloud to Edge

Dr. Charlie Su

Co-Founder, President and CTO, Andes Technology

10:00 - 10:20

Silicon Lifecycle Management: Trends, Challenges and Solutions

Dr. Yervant Zorian
Chief Architect and Fellow, Synopsys

10:20 - 10:40

Investing in Semiconductor Startups: Driving Innovation and Growth

Kay Enjoji

President, TEL Ventures

10:40 - 11:00

The Growing Importance of The Semiconductor Industry

Lee Harrison

Director Tessent Product Marketing, SIemens EDA

IP & Cores Track
(click here for detailed track agenda)
Shin (Shimon) Raviv, Director Product Marketing, Weebit Nano
​Ilan Sever, VP R&D, Weebit Nano


11:40 - 12:00

Embedding the Right Secure Hardware Into Your Design is Essential to Obtain the Right Certification Level

Serge Maginot

CEO, Tiempo Secure

12:00 - 12:20

Accelerating Compute…It’s Not Just About Hardware!

Rob Fisher

Director of Product Management, Imagination

12:20 - 12:40

High-efficiency NPU IP for the Generative AI Era
Eli Tom

Architecture Simulation Team Leader, CEVA

12:40 - 13:00

Functional Monitoring and Performance Analysis With Tessent Embedded Analytics

Devan Sharma

Siemens EDA

13:00 - 13:20

The Edge of Tomorrow: Intelligent Compute to scale AIoT

Rob Telson

VP Ecosystems and Partnerships, BrainChip

13:20 - 14:20

Lunch, Exhibition Visit

14:20 - 14:40

Optimizing Silicon Health and Cost Using Monitoring and Analytics Throughout Product Lifecycle

Avi Braun

Business Development Manager, Hardware Analytics and Test for Europe, Synopsys

14:40 - 15:00

The New Chiplet Ecosystems Enabling Today’s Solutions
John Lupienski

VP Product Engineering, Blue Cheetah

15:00 - 15:20

Alphawave Semi - Unleashing a New Era of AI Connectivity

David Kulansky

Director of Product Marketing, Alphawave Semi

15:20 - 15:40

SoC & Chiplet Infrastructure IP: The SignatureIP Vision and Implementation

Avi Plotnik

Director of Field Applications Engineering, Israel, Signature IP

Front-end Design & Verification Track
(click here for detailed track agenda)

Sponsored by:
Moderator: Alex Marin, RnD Team Leader, AMIQ EDA


11:40 - 12:00

Presilicon Validation - When Massive Data Capture is a Must

Frederic Leens

CEO, Exostiv Labs

12:00 - 12:20

Connectivity & Glitch Sign-Off Case Studies

Oren Katzir

Vice President Application Engineering,  Real Intent

12:20 - 12:40

On-the-Fly Incremental Linting for Design and Verification Code using Verissimo in the DVT IDE

Alex Marin

RnD Team Leader, AMIQ EDA

12:40 - 13:00

Artificial Intelligence Powered NoC IP-Vision of the Future

Nitin Kishore

CEO, Truechip Solutions

13:00 - 13:20

Overcoming RISC-V Customization Quality Hurdle With Formal Verification

Gerardo Nahum
Application Engineer Manager, DVT Formal Solutions, Siemens EDA

13:20 - 14:20

Lunch, Exhibition Visit

14:20 - 14:40

No Defenestration, Please! A Fresh Perspective on the Verification Gap

Oron Port
CEO, DFiant

14:40 - 15:00

How to Sign-off Cryptographic Hash Implementations With Generated Formal Assertions

Dr. Tobias Ludwig

Founder & CEO, LUBIS EDA

15:00 - 15:20

Leveraging Formal Verification to Boost Chip Development Process

Shirit Schvartzblat
Senior Director, Chip Design, Nvidia

15:20 - 15:40

Seamless Integration of Formal Verification

Alon Rot

Senior VLSI Team Lead, CEVA


Post Silicon Track
(click here for detailed track agenda)
Moderator: Ronen Livni, Director Product & Test Engineer Manager, Vayyar

post silicon
physical design

Physical Design Track
(click here for detailed track agenda)
Sponsored by:

Moderator: TBD

Siemens logo

11:20 - 11:40

Multi-die System Design and 3D, The Next Big Step in IC Evolution
Leon Rabinovich
Senior AE, Synopsys

11:40 - 12:00

Under the Hood of OpenFPGA

Pierre-Emmanuel Gaillardon
CTO, Rapid Silicon

12:00 - 12:20

New Layout Methodologies and ​Advanced Node Automation
Yonatan Kliger
Application Engineer Director, Cadence

12:20 - 12:40

Intrinsic Intelligent P&R For Advanced Node Designs

Nahum Rozen

Aprisa P&R Application Engineering Specialist, Siemens EDA

12:40 - 13:00

Power (Source) Aware Floor Planning
Jorge Antonio Araiza Martinez
Technical Layout Lead, ICMASK

13:00 - 14:00

Lunch, Exhibit Viewing

14:00 - 14:20

Why Advanced Packaging & 3D Integration Does Matter to Everybody

Anna Fontanelli

Founder & CEO, Monozukuri

14:20 - 14:40

30 Thousand Wafers in Your Browser
John O'Donnell
Founder and CEO, yieldHUB

14:40 - 15:00

3D IC Test Challenges and Solutions

Martin Dresler

Director Performance Digital Business, Advantest

15:00 - 15:40

Advanced Packaging & Challenges for Test

George Harris

Vice President, Global Test Services, Amkor Technology

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