Post SIlicon Track
Moderator: Ronen Livni, ATE Test and Product Manager, Vayyar
13:00 - 14:00 : Lunch, Exhibit Viewing
Founder & CEO
14:00 - 14:20
Why Advanced Packaging & 3D Integration Does Matter to Everybody
With the continuous shrinking of integrated circuit size and the continuous evolution of technological process, Moore's Law is gradually entering the bottleneck, so at present, 3D integration technology has become a new hope to solve the industry dilemma. Heterogeneous ICs such as sensors, memories, microprocessors and RF can be easily combined by using programmable silicon substrates and advanced packaging technologies. However, new tools, methodologies and flows are required to automate the design process of to obtain a single chip with customized function combination economically, quickly and efficiently.
Anna is a silicon executive bringing extensive know-how and more than 35 years of hands-on experience in the research, design and industrialization of innovative EDA solutions in the deep-submicron silicon technologies space, having worked at Mentor Graphics, where she led the Marketing team who developed I/O Designer and at STMicroelectronics Central R&D, where she led the development, and the deployment of 3 generation of IC & Package co-design tools.
In 2015, she funded Monozukuri, an Italian EDA company, delivering disruptive software solutions to enable and accelerate the 2.5D & 3D-design of next generation electronic products.
Anna holds a master degree in Mathematics from the ‘Università degli studi di Milano’, Italy and is the author / co-author of several papers (11 regular + 1 invited) and patents (2).
Founder and CEO
14:20 - 14:40
30 Thousand Wafers in Your Browser
I'll start with a story about Steve Jobs
"Steve Jobs first introduced this iconic device (the slide will show an iPod) in 2001, at a small press event at the Town Hall auditorium at Apple's former Infinite loop headquarters; pulling it out his pocket, he famously pitched it with the slogan: “1,000 songs in your pocket.”
and the presentation will explain what it's like to have all your wafer data in your browser, which summarises yieldHUB.
John O'Donnell is founder and CEO of yieldHUB. He graduated in BE (Elec) from University College Cork in Ireland and then worked
in a large multinational semiconductor company in various roles in Product and Test Engineering. His particular focus was on data and in particular how data can be used for yield improvement and improving operational efficiency in testing semiconductors.
John started yieldHUB (formerly MFG Vision) in 2005. The focus of yieldHUB is instant access to data across manufacturing and fast, effective analysis.
The company has close to 40 multinational fabless and IDM customers for their thin-client yield management platform. John has a wife and four children and in his spare time likes to play golf and chess.
Director Performance Digital Business
14:40 - 15:00
3D IC Test Challenges and Solutions
Heterogenous integration is further accelerating the drive towards more processing power and Exascale Computing. Such computation power is necessary for advanced AI and machine learning applications such as big data analysis, autonomous cars and pattern recognition.
3D silicon stacking and advanced packaging open the door to a new era of innovation. Stacking individual die/wafer layers vertically offers several advantages in terms of shorter electrical signals between dies, lower overall power consumption, faster signal transitions, higher integration and space savings. This presentation discusses the various trends and challenges for testing high performance computation devices and describes technical solutions how to improve test quality while managing cost of test.
Martin Dresler, MSEE and MBA, works at Advantest Europe and has more than 20 years of ATE experience in the areas of mixed-signal, high-speed digital, high-speed memory and RF in different positions. He is Director of Performance Digital Business and leading the worldwide performance digital team activities including AI and high-performance compute.
Vice President, Global Test Services
15:00 - 15:40
Advanced Packaging & Challenges for Test
Exciting market mega trends are driving growth in advanced packaging. As die sizes increase, there is a higher probability of being impacted by inherent wafer defect densities resulting in overall lower yield. Realizing this, integrated circuit (IC) designers split the functionality of the large die into small chiplets or dielets. Further, platform and system integrators have increasingly found the need to integrate functional blocks that must be fabricated on distinctly different fabrication processes. Advanced packaging enables the path to integrate chiplets within a single package. Heterogeneous integration (HI) is a powerful design innovation that allows tighter integration and, in some cases, improved power performance at the system level.
Multi-die packages introduce unique testing challenges where a test engineer needs to have a broad spectrum of expertise covering the testing of radio frequency (RF) devices, mixed-signal & analog, high-speed digital, narrow and wide interface memories, photonics, sensors, power control & distribution, embedded passives and various interconnect technologies. This expertise must be applied to wafer probe, burn-in (BI), final test (FT) and system-level test (SLT).
Chiplet’s electrical, mechanical and thermal constraints impact the package assembly technology. These in turn impact the challenges of package-level testing. This presentation explores recent examples and provides insight into the challenges of testing and test methodologies that allow data collection on present packaging implementations, which results in continuous improvement for future designs.
George joined Amkor in 2020 and is currently responsible for Global Test Services operations. Prior to joining Amkor, George led teams and factories for II-VI Inc on VECSEL GaAs products for 3D imaging and preceding that spent 30 years at Texas Instruments engaged in work on memory, analog and SOC products. He holds six US and EU patents on circuit design, wafer fab processing, test and manufacturing controls. George earned masters and bachelor’s degrees in electrical engineering from Syracuse University.