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Front-end Design & Verification

Item List

Liberating Functional Verification from Boolean Shackles

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Oren Katzir

Vice President, Applications Engineering, Real Intent

Emerging Challenges and Solutions in Functional Safety and Security for Automotive, AI, Data Center, and Space Chips

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Jamil R. Mazzawi

CEO, Optima Design Automation

DV Has a Playbook - Why Doesn’t Formal?

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Roy Frank

Verification Technical Leader, AI-Fabrics

Guardrailing AI with Formal Verification: Abstract Models as the Anchor of Trust

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Dr. Tobias Ludwig

CEO, LUBIS EDA

Is RTL Holding Back AI Hardware Generation?

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Oron Port

CEO, DFiant

Accelerating High-Performance SoC Development with Siemens EDA and Arm: A Software-Aware Verification IP Approach

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Ofer Shragay

Verification Application Engineer, Siemens EDA

From GVIM/EMACS to Modern IDEs: A Verification Engineer's Journey with DVT

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Netanel Miller

HW Verification Team Leader, Texas Instruments

Leveraging Formal Verification to Boost Chip Development Process

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Eytan Dreyfus

Formal Verification Director, NVIDIA

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