Agenda
November 11, 2025
SemIsrael Expo 2025 is packed with professional content; great keynote speakers, and 4 professional tracks:
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IP & Cores
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Front-end Design & Verification
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Post Silicon
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Physical Design
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Professional tracks presentations will start after a general assembly session.
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Event agenda - General
08:00 - 09:00
Breakfast, Exhibition Visit
09:00 - 11:00
11:00 - 11:40
Break, Exhibition Visit
11:40 - 13:00
Professional Tracks - Part 1 (IP & Cores, Front-end Design & Verification, Post Silicon)
13:00 - 14:10
Lunch, Exhibition Visit
14:10 - 15:30
Professional Tracks - Part 2 (IP & Cores, Front-end Design & Verification, Physical Design)
15:30
Summary, Lucky Draws
Keynote Speakers (General Assembly)
(click here for detailed general assembly agenda)
09:00 - 09:20
Welcome Notes
Shuka Zernovizky
Founder, SemIsrael
09:20 - 09:40
Design for AI and AI for Design - A New Era of Design Excellence
Corporate VP, System Verification and AI Technology, Cadence
09:40 - 10:00
Powering Intelligent General-Purpose Computing with RISC-V
President and CTO, Andes Technology
10:00 - 10:20
AI/ML at the Forefront of Semiconductor Evolution: Enhancing Design, Efficiency, and Performance
Dr. Yankin Tanurhan
Senior Vice President, Engineering, Synopsys
10:20 - 10:40
10:40 - 11:00
IP & Cores Track
(click here for detailed track agenda)
Moderator:
Shin (Shimon) Raviv, Director Product Marketing, Weebit Nano
11:40 - 12:00
Seeding Trust: Hardware-Based Random Number Generation for Cryptographic Security
CEO, Xiphera
12:00 - 12:20
12:20 - 12:40
NPU IP Hardware Shaped Through Software Insights and Use-Case Analysis
Ido Gus
Deep Learning Senior Team Leader, Ceva
12:40 - 13:00
In-system Test, a Critical Part of Any SLM Solution
Director Product Marketing Tessent, Siemens EDA
13:00 - 14:10
Lunch, Exhibition Visit
14:10 - 14:30
Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplets
VP of Product Management and Marketing, Arteris
14:30 - 14:50
Next Gen Interfaces & Protocols for Evolving Architectures in AI driven Data Centers
Applications Engineering, Director IPG, IP Group, Synopsys
14:50 - 15:10
Overcoming Density and Power Barriers in Advanced Node SRAMs
Dr. Robert Giterman
Co-Founder and CEO, RAAAM Memory Technologies
15:10 - 15:30
Post-quantum Algorithms MS-KEM and MS-DSA Protected Against Physical Attacks, in Hardware and in Software
Chief Innovation Officer, FortifyIQ
Front-end Design & Verification Track
(click here for detailed track agenda)
Sponsored by:
Moderator: Dr. Reuven Dobkin, CTO, vSync Circuits Ltd.
11:40 - 12:00
Leveraging Formal Verification to Boost Chip Development Process
Formal Verification Director, NVIDIA
12:00 - 12:20
Liberating Functional Verification from Boolean Shackles
Vice President, Applications Engineering, Real Intent
12:20 - 12:40
From GVIM/EMACS to Modern IDEs: A Verification Engineer's Journey with DVT
HW Verification Team Leader, Texas Instruments
12:40 - 13:00
Emerging Challenges and Solutions in Functional Safety and Security for Automotive, AI, Data Center, and Space Chips
CEO, Optima Design Automation
13:00 - 14:10
Lunch, Exhibition Visit
14:10 - 14:30
Accelerating High-Performance SoC Development with Siemens EDA and Arm: A Software-Aware Verification IP Approach
Ofer Shragay
Verification Application Engineer, Siemens EDA
14:30 - 14:50
Is RTL Holding Back AI Hardware Generation?
Oron Port
CEO, DFiant
14:50 - 15:10
Guardrailing AI with Formal Verification: Abstract Models as the Anchor of Trust
Founder & CEO, LUBIS EDA
15:10 - 15:30
Post Silicon Track
(click here for detailed track agenda)
Moderator: Daniel Lipovitch, Director of Marketing, Weebit Nano
11:40 - 12:00
Get Ready for Production Test Before Silicon With an ATE Digital Twin
Meir Gellis
CEO, TestInsight
12:00 - 12:20
Solving the Cooling Challenges from Chip to Data Center Level by Numerical Simulation
Dr. Eldad Levy
CEO, CAS - Computerized Analysis & Simulations Ltd.
12:20 - 12:40
Advanced Metrology Solutions for AI Packaging Processes
Yenon Ben-Haim
Application Tech Lead, NOVA
12:40 - 13:00
Future-Proof Your Lab: Strategies & Solutions for Modern R&D Spaces
CEO, DLVS Consultancy
13:00 - 14:10
Lunch, Exhibition Visit
Physical Design Track
(click here for detailed track agenda)
Sponsored by:
Moderator: Asaf Moreno, Calibre Application Engineer, Siemens EDA
14:10 - 14:30
Calibre Design - Global View Updates, 3DIC , AI
Calibre Application Engineer, Siemens EDA
14:30 - 14:50
Using Cadence Voltus and Voltus Insight Technologies For Overcoming the EM-IR Challenges of Advanced Nodes
Ronen Stilkol
Application Engineer Architect, Cadence
14:50 - 15:10
15:10 - 15:30
Breaking the Memory Wall: Scaling AI Inference with Credo OmniConnect
SVP Product, Credo