Physical Design Track

Moderator: Asaf Moreno, Calibre Application Engineer, Siemens EDA

13:00 - 14:10 : Lunch, Exhibition Visit

Gal Gottlieb

EMEA Calibre Application Engineer

Siemens EDA

14:10 - 14:30

Calibre Design - Global view updates, 3DIC , AI

Abstract will be soon published

BIO:

Gal holds a BSc in Mechanical Engineering from Tel Aviv University.
Gal has over 20 years of industry hands-on experience in VLSI Backend CAD, Covering a wide range of products, from dynamic startups to large, established companies.
Gal recently added experience and knowledge in Silicon Photonics.
Gal supports Siemens Calibre users, ensuring they receive all the assistance and guidance needed to optimize their workflows and achieve their goals.

14:30 - 14:50

Using Cadence Voltus and Voltus Insight Technologies For Overcoming the EM-IR Challenges of Advanced Nodes

Voltus delivers fast, full-chip power integrity analysis for even advance nodes most complex designs.
With InsightAI, generative AI predicts and resolves IR drop issues early during P&R stage, boosting PPA and accelerating closure.
The Voltus Training Kit (VTK) makes onboarding effortless with a ready-to-run, methodology-based flow that supports both Voltus and InsightAI

BIO:

Ronen Stilkol is an AE Architect at Cadence Design Systems, bringing extensive expertise in the field of electronic design automation (EDA) and semiconductor design.
In his role, he works closely with customers to understand their unique technical requirements and guide them in effectively utilizing Cadence's cutting-edge software to achieve their design goals.
His focus is at PI/SI verification using Voltus, for that he created VTK (Voltus Training Kit) that accelerate costumers ramp up and productivity with minimal efforts and resources

Ronen Stilkol

Application Engineer Architect

Cadence

Leon Rabinovich

Principal Engineer

Synopsys

14:50 - 15:10

Fusion Compile AI-Drive Optimization

AI assisted design implementation is the next generation of tools, designed to accelerate the chip designers’ time to market, while dealing with overwhelmingly increasing design complexity. Synopsys is a pioneer in AI-driven electronic design automation (EDA), and we recently bolstered the AI capabilities of our Fusion Compiler via native integration with DSO.ai (Design Space Automation). With dynamic, adaptive flows powered by AI, the solution is able to automate decision making, optimize power, performance, and area (PPA), and deliver faster, more effective results.

BIO:

Leon Rabinovich holds an Electrical Engineering Degree from the Tel Aviv University. He has over 30 years of experience in the industry, filling the positions of an BE R&D engineer as well as an BE FAE for multiple semiconductor companies.

15:10 - 15:30

Breaking the Memory Wall: Scaling AI Inference with Credo OmniLink

AI inference workloads are increasingly constrained by memory bandwidth and capacity and less by compute . Traditional memory architectures struggle to meet the demands of large-scale models.
In this webcast, we introduce Credo Link Fusion, a revolutionary memory interface that leverages 112G VSR serdes to dramatically increase memory density and bandwidth with power efficiency. We will explore how Credo Link Fusion enables late DRAM binding, supports future LPDDR6 migration, and unlocks new scale-up capabilities for XPU vendors and system integrators.

BIO:

Don Barnetson is the SVP of Products at Credo with a focus on product definition and customer engagement. Prior to Credo, Don was CTO at Lunera, an IoT Platform company. Don received his BSEE from the University of Calgary and his MBA from UC Berkeley. He holds 26 US patents.

Don Barnetson

SVP Product

Credo