Front-end Design &Â Verification Track
Sponsored by:
Moderator: Dr. Reuven Dobkin, CTO, vSync Circuits Ltd.
Eytan Dreyfus
Formal Verification Director
NVIDIA
11:40 - 12:00
Leveraging Formal Verification to Boost Chip Development Process
Over the past two decades, formal verification (FV) has increasingly influenced the chip design development process. At Nvidia's networking division, we have refined this practice into a comprehensive methodology, supported by management directives. This approach has maximized the benefits of FV, enabling us to accelerate time-to-market and deliver exceptionally high-quality results. Furthermore, we maintain an efficient verification process by ensuring seamless coordination with our simulation teams.
BIO:
With 18 years of expertise in the field of hardware formal verification in Mellanox and later Nvidia, Eytan has managed various FV projects and developed FV methodologies and tools.
12:00 - 12:20
Liberating Functional Verification from Boolean Shackles
Functional verification consumes a significant portion of engineering resources. According to a recent study by Wilson Research Group, design engineers spend approximately 46% of their time on verification, while verification engineers dedicate their entire focus to it. Although logic and functional bugs are the leading cause of silicon re-spins, clock-related issues closely follow. With increasing design complexity—especially in clocking, power management, and resets—formal and static verification methods have become essential for achieving comprehensive verification of complex designs.
BIO:
Oren Katzir leads Real Intent’s Application Engineering (AE) team @ Real Intent. He brings to this position more than 20 years of experience in engineering management, SoC and ASIC design, and development of SoC design tool flows. Previously, Oren was an engineering manager at Intel, leading an SoC engineering team. He also held engineering management positions at Sagantec, Silicon Design Systems, Transchip and Silicon Value. Oren holds a BSEE in computer engineering from Technion-Israel Institute of Technology.
Oren Katzir
Vice President, Applications Engineering
Real Intent
Netanel Miller
HW Verification Team Leader
Texas Instruments
12:20 - 12:40
From GVIM/EMACS to Modern IDEs: A Verification Engineer's Journey with DVT
This talk explores a personal journey from traditional text-based hardware development to modern IDE-driven workflows, highlighting the transformative impact of the DVT IDE. It showcases key features—code navigation, UVM support, visualization tools, and debugging capabilities—that have significantly enhanced productivity and verification quality. The session concludes with a forward-looking perspective on DVT’s integration with VS Code, Git GUIs, and LLM-based assistants, illustrating how these tools collectively address the growing complexity in hardware design and verification.
BIO:
Netanel Miller is a recognized verification expert and technical leader at Texas Instruments with 9+ years of experience in SOC-level verification architectures and methodologies, who pioneered modern development workflows and AI adoption initiatives across the organization.
Jamil R. Mazzawi
CEO
Optima Design Automation
12:40 - 13:00
Emerging Challenges and Solutions in Functional Safety and Security for Automotive, AI, Data Center, and Space Chips
Abstract will be soon published
BIO:
Jami Mazzawi has over 32 years’ experience in the semiconductor and EDA industries across Silicon Valley, Israel, and Europe. He has held engineering, sales, and managerial positions at Ornet Data Communication, Verisity Inc., Rambus, Sun Microsystems, Jasper Design Automation, and now Optima. With a successful track record developing, promoting, and selling disruptive technologies that include advanced verification solutions and leading automotive development products, Jamil authored over 12 patents in related fields. Jamil holds a B.Sc. in Computer Engineering from the Technion, Israel and an MBA from San Jose University, CA.
Jamil is a Functional Safety Certified Semiconductor Expert (FSCSE by TÜV NORD).
13:00 - 14:10 : Lunch, Exhibition Visit
Ofer Shragay
Verification Application Engineer
Siemens EDA
14:10 - 14:30
Accelerating High-Performance SoC Development with Siemens EDA and Arm: A Software-Aware Verification IP Approach
In the race to deliver high-performance infrastructure SoCs, time-to-market is a critical differentiator. Siemens EDA, in collaboration with Arm through the Arm Total Design (ATD) ecosystem, presents a robust methodology that accelerates the development and verification of Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs. This presentation showcases how the integration of Arm Fast Models, Siemens Software Aware Verification IP (VIP), and industry-leading protocol Verification IP enables shift-left full-system verification. Attendees will learn how this approach supports early software bring-up—including full UEFI and Linux bootup—while validating the RTL design and complex protocols like PCIe7.0, CXL 3.1, HBM, and UCIe 3.0 in a pre-silicon environment. Early co-simulation of hardware, firmware, and software with simulation's fast turnaround time so that critical system behaviors are validated early, reducing integration risks and accelerating debug cycles. It sets up the transition to later project stages using hardware emulation or prototyping for larger scale workload and stress testing, with pre-validated software and firmware - dramatically shortening the path from design to deployment, by delivering accelerated confidence.
BIO:
As an Application Engineer at Siemens, I specialize in verification, driving the successful deployment of new technologies, languages, and tools at customer sites. With 25 years of experience, I've honed my expertise across Sital Technology, Mentor Graphics, and Siemens. My focus is on empowering customers with cutting-edge solutions and seamless integration.
14:30 - 14:50
Is RTL Holding Back AI Hardware Generation?
As chip design grows in cost and complexity, traditional verification methods are struggling to keep pace. AI promises to transform the process, but the critical question remains: what is the right abstraction layer for hardware generation?
This talk explores why RTL may not be the best intermediate, and what a new alternative could look like. By rethinking design and verification flows, we can unlock faster, more scalable, and cost-effective chip development.
BIO:
Oron is the CEO and Co-Founder of DFiant, a company helping teams modernize hardware design with scalable and reliable DevOps and FPGA solutions. His research at Technion and Cornell focused on high-level hardware design abstractions and languages—experience that now fuels his mission to reshape how we think about chip design and verification.
Oron Port
CEO
DFiant
Dr. Tobias Ludwig
CEO
LUBIS EDA
14:50 - 15:10
Guardrailing AI with Formal Verification: Abstract Models as the Anchor of Trust
AI accelerates creativity in chip design, while verification demands rigor and determinism. To ensure both can coexist reliably, they must share a single, consistent ground truth. Abstract models serve as this foundation. Using formal verification, we can rigorously connect these models to the RTL level. In this talk, we demonstrate how our property generator establishes this link, enabling AI-assisted design and verification to stay aligned, consistent, and trustworthy.
BIO:
Dr. Tobias Ludwig is the CEO and co-founder of LUBIS EDA. A die-hard formal engineer with 10+ years in formal verification, he’s spent the last five years as CEO scaling LUBIS EDA from a four-person idea to a 35-person company serving complex silicon teams worldwide. Tobias leads with product focus and customer service, bringing formal methods out of academia and into day-to-day sign-off for high-risk designs.
15:10 - 15:30