Physical Design Track

Moderator: Nahum Rozen, Aprisa P&R Application Engineering Specialist, Siemens EDA

Leon Rabinovich

Senior AE

Synopsys

11:20 - 11:40

Multi-die System Design and 3D, The Next Big Step in IC Evolution

The growing use of High Bandwidth Memory (HBM3) and Universal Chiplet Interconnect Express (UCIe) and the disaggregation of very large dies into chiplets have enabled a substantial reduction in multi-die system design cost. But the real payoff with multi-die design is 3D, where vertical integration delivers higher system performance with increased density and energy efficiency in a smaller physical form factor. In this session, Synopsys will present its solution enabling chipmakers in mobile, HPC, and AI to reap the benefit of multi-die system design and 3D.

BIO:
Leon Rabinovich has an Electrical Engineering degree from the Tel Aviv University.
He has been a Synopsys AE during the past 15 years with a total Semiconductor industry experience of more than 25 years.

11:40 - 12:00

Under the Hood of OpenFPGA

In this talk, we will introduce the OpenFPGA framework whose aim is to generate highly-customizable Field Programmable Gate Array (FPGA) fabrics and their supporting EDA flows. Following the footsteps of the RISC-V initiative, OpenFPGA brings reconfigurable logic into the open-source community and closes the performance gap with commercial products. OpenFPGA strongly incorporates physical design automation in its core and enables 100k+ look-up tables FPGA fabric generation from specification to layout in less than 24h with a single engineer effort.

BIO:
15 years of innovation in the field of FPGA architectures and EDA tooling. Associate Professor and Associate Chair of Electrical and Computer Engineering (ECE) at The University of Utah and Principal Investigator of OpenFPGA. Recipients of prestigious NSP CAREER award, DARPA Young Faculty Award, IEEE CEDA Ernest Kuh award and ACM SIGDA ONFA award.

Pierre-Emmanuel Gaillardon

CTO

Rapid Silicon

Yonatan Kliger

Application Engineer Director

Cadence

12:00 - 12:20

New Layout Methodologies and Advanced Node Automation

The industry-leading Cadence® Virtuoso® custom IC layout design tools are designed to accelerate your physical layout implementation productivity, enabling you to achieve faster design convergence with higher quality and more differentiated silicon.

The Virtuoso platform is the industry’s most silicon-proven, comprehensive, custom IC design platform, trusted in taping out thousands of designs each year for more than 25 years, with a wide range of design styles, from advanced full custom polygon editing through flexible schematic-driven layout and through constraint-driven assisted layout or automated full custom layout.

In this presentation we will describe new methodologies and a comprehensive design flow in Virtuoso layout tool to help you manage the growing complexity and boost your productivity for analog, RF and custom logic with:

· Advanced node design migration

· Layout automation and productivity

· RFIC and module 2.5D/3D co-design and simulation

· In-design DRC, sim/electrically driven design

· Virtuoso Electronic-Photonic Design

BIO:
Yonatan Kliger is a director at Cadence leading the Israel custom IC application engineering team.

His team responsibility is managing the engagement and support of Virtuoso products inc.

Cadence® Spectre® simulation suite, Photonics, Liberate and all of Cadence System products.

He is focused on customers success with wide experience in custom design and simulation including mixed signal verification and modeling.

Prior to that he was an analog and mixed signal designer for 10 years in global semiconductor companies and startups.

Nahum Rozen

Aprisa P&R Application Engineering Specialist

Siemens EDA

12:20 - 12:40

Intrinsic Intelligent P&R For Advanced Node Designs

Many of today’s IC devices aim for portability, and therefore require fast user interaction response and long-lasting batteries that can only be achieved in a low power system. Cloud and data storage solutions also require thoughtful attention when it comes to reducing power, for increased reliability and to extend the life of the devices.
All of this puts power consumption front and center during chip design and implementation. Designers must balance tradeoffs in reducing both dynamic power and leakage power, while maintaining the suite of added functionality that users have come to expect from those devices. A variety of techniques are available to achieve low power designs, but knowing how to best implement them can be daunting.
Aprisa’s low power solution integrates all of the features necessary to achieve best-in-class low power chips, all while maintaining an easy to use, intuitive design flow that our customers have grown to expect.

BIO:

Nahum has over 30 years of experience in the VLSI area in all its phases and in advanced design nodes. He has served in many design and managerial roles including close contact with leading FABs.

Jorge Antonio Araiza Martinez

Technical Layout Lead

ICMASK

12:40 - 13:00

Power (Source) Aware Floor Planning

The Challenges:
Making a floorplan is one of the main tasks that a layout engineer has, the implementation of the floorplan will directly affect different variables:

Area
Matching of devices
Density of base layers

Although these are the main and more tangible variants that the floorplan affects, there are some others that will affect the quality and efficiency of the physical implementation of the circuit:

Power Structure
Routing area
Schedule

With the “Power Aware Floor planning” methodology we will be able to have a good understanding of our power structure from the beginning for both Analog and Digital Blocks. In the case of only digital Blocks, we found that with this methodology we can make good quality layout, fast, easy, and even save area compared to circuits provided by the foundries.