IP & Cores Track
Shin (Shimon) Raviv, Director Product Marketing, Weebit Nano
Ilan Sever, VP R&D, Weebit Nano
Technical Account Manager, IC Verification & Validation
11:20 - 11:40
Expanding DFT Automation for 2.5D / 3D IC
Abstract - TBD
Itamar has over 20 years of technical experience in the semiconductor industry. He has supported a multitude of local & international customers on a wide range of solutions targeting DFT and RTL->GDSII flow. Itamar has also successfully fulfilled various roles within chip design companies that include Digital / Analog layout design, Place & Route and CAD as well as developing personalised tools in order to achieve faster chip development.
11:40 - 12:00
A Trusted Partner to Watch Your Back and Pave Your Path to Success
When engaging on a complex high-end project, there is merit to creating a team of trusted resources that transcends your company. This team will watch your back and will help you through the hurdles of your design. Complex IP blocks will be required and you will want to have your IP provider beside you at the dawn of the design, during integration and debug, when you approach tapeout, and when your silicon is back. A trusted partner such as OpenFive will do all that and may outsource large parts of your design and supply chain management to leave you with the peace of mind required to bring over the REAL contribution of your company to our world.
This presentation introduces OpenFive, a wholly owned subsidiary of SiFive and a provider of key technology IP, design technology and supply chain management. We will introduce the company, its capabilities, and the disciplines in which you can trust OpenFive as your trusted design partner who will watch your back and pave your path to success - from dawn to dusk.
Costas Conistis is a seasoned semiconductor executive now serving as the Sr. Director of Sales for EMEA and named accounts worldwide. He has almost 25 years of executive customer-facing experience, including over 20 years at Synopsys as the Regional Manager of Canada and the Northern USA for Synopsys customer support group. Most recently, he has served as the Director of Marketing and Sales for Rianta Solutions which Marvell acquired. Previous experience includes leading and designing the next generation of IC for Newbridge Networks, which Nokia acquired.
Costas holds a B.A Sc in Electrical Engineering (Honours) from the University of Waterloo.
Sr. Director Sales
VP Sales and Solutions Architecture
Flex Logix Technologies
12:00 - 12:20
Enabling Software Developers with Software Acceleration with Reconfigurable Hardware Functions
Today many ASIC, DPU, CPU and applications processors leverage companion FPGAs for acceleration. By integrating eFPGA IP, software developers can directly apply application specific accelerators to improve performance, maximize compute density, and dynamically change them via software as workloads change. Hardware acceleration can now be put in the hands of software developers allowing companies to extend the lifecycle of their products, modify features over time, and at the same time reduce system cost and power.
Andy is responsible for Flex Logix’s Sales. He has over 20 years of sales and sales management experience starting as Account Sales Manager at Motorola Semiconductor then Director Strategic Accounts at Arm. Moved to ARC as VP Sales, North America and continued ARC sales responsibilities when ARC was acquired by Virage and then Synopsys.
Field Application Engineer
12:20 - 12:40
SiFive Automotive, Transforming Safety-critical Applications With RISC-V Processors
In a rapidly evolving market, automakers are looking to meet critical needs for current and future digital vehicle applications like infotainment, cockpit, connectivity, ADAS, and electrification.
RISC-V offers crucial energy efficiency, simplicity, security, and software flexibility benefits, supported by a growing ecosystem.
Today’s high-end applications and real-time processors are demonstrating high performance, with the lowest area and power consumption, to meet vehicle specific needs for safety, security, and performance.
SiFive’s broad SiFive AutomotiveTM product family is an end-to-end portfolio of safety-capable RISC-V IP designed to combat these challenges being faced by auto designers.
This presentation will highlight the benefits that RISC-V brings to automotive with examples of how the SiFive Automotive product family is already being used by semiconductor suppliers to take advantage of the simplicity of a single open standard RISC-V ISA, and code portability and reusability throughout the full range of required performance levels for these varied functional safety and secure computing applications.
I'm Field Application Engineer in the microprocessor domain specializing in embedded software.
I've worked in several semiconductor companies where I was responsible for the firmware design, implementation, and bring up.
The last couple of years I'm working in a customer-facing role, bringing customer requirements into microprocessor-based SoC implementations.
Currently, I work closely with a wide range of customers adopting the emerging RISC-V Architecture..
Wim van Seters
Sales Director Europe & Israel
12:40 - 13:00
Ultra-low Read Energy OTP
I-fuse®: Revolutionary OTP technology
Wim has more than 25 years experience in the semi-conductor industry, and has worked for more than 10 in various positions and locations in Intel. Since 15 years Wim, as independent sales representative, has been working with various IP and EDA companies for sales in Europe and Israel. One-time-programmable (OTP) technologies have been part of his portfolio since the start.
13:00 - 14:00 : Lunch, Exhibit Viewing
Head of Solution Architectures
14:00 - 14:20
A Scalable Framework for Fast Design Space Exploration of AI Workloads in [Complex] SoCs
SoC developments are time pressured, resource constrained and face considerable risk. Add automotive ISO26262 ASIL-D requirements plus heterogenous compute for vision & AI processing and the challenge associated with ASIC implementation rises to new levels.
Solving the challenges, Sondrel applied latest SoC architecture concepts to develop a framework which defines a set of processes for capturing engineering requirements, developing a concept architecture and analysis of architecture performance using SystemC TLM models.
The approach was designed to enable optimal scaling of performance which support a wide range of compute requirements.
Several reference SoC architectures have been derived from the framework, each targeting specific application use cases. For automotive applications, the reference architecture embedded in Sondrel’s SFA350-A platform provides the necessary feature set and scalability options to support a wide range of automotive SoC derivatives.
Automotive AI applications employ ever more sophisticated neural network algorithms, such as the Vision Transformers (ViT), which have out-performed CNNs and RNNs on several benchmarks. This paper explores the requirements of complex AI workloads, such as the ViT, in tandem with the methodology and tools required to evaluate compliance to system-level requirements of an SoC architecture. Rapid design space exploration is accomplished using performance models of a commercially available NPU & companion DSP, NoC interconnect and LPDDR5x to determine an optimal hardware configuration derived from SFA350-A.
Paul Martin is Head of Design Architecture at Sondrel and is responsible for technical sales worldwide. Paul has been working with Sondrel for 7 years, having initially joined to lead Sondrel’s design and verification services business.
He has gone on to manage Sondrel’s EMEA design centres and SoC architecture team, developing Sondrel’s SoC reference architectures. Prior to joining Sondrel, Paul has held senior positions at Arm and NXP, where he worked in the CTO organisation, leading advanced SoC development, IP design, and design methodology programs.
14:20 - 14:40
Actionable Insights Through Silicon Lifecycle Monitoring and Analytics
The emerging paradigm shift towards Silicon Lifecycle Management and how it is changing the way the Semiconductor Test and SoC communities think about device and system performance, silicon health and predictability. The new era of SLM has opened up opportunities for developing new, insightful monitoring and analytics technologies that are now providing solutions to the optimization challenges faced by test teams, chip and system developers across a wide range of applications. Silicon Lifecycle Management is one of the most exciting areas of evolution for the semiconductor industry and based on the value it brings to each phase of the device lifecycle from early design right through to in-field. As Silicon Lifecycle Management continues to gain momentum it is just a matter of time before adopting and using SLM is standard procedure on every project.
The Synopsys Silicon Lifecycle Management family has been developed to improve silicon operational metrics at every phase of the device lifecycle and has been built on a foundation of enriched in-chip observability, analytics and integrated automation. Embedded monitors enable deep insights from silicon to system. Meaningful data is gathered at every opportunity for continuous analysis and actionable feedback.
Avi Braun is Business Development Manager for Hardware Analytics and Test for Europe at Synopsys.
Avi works at Synopsys for almost 12 years now in various of key roles including Leading Design Services, Customer support and Customer Solutions.
Previously Avi has worked at Zoran Corporation for 10 years as a VLSI Manager, handling VLSI projects execution and responsibilities.
Avi is going to talk about one of the most exciting and challenging topics in today’s semiconductor industry - Actionable-Insights-Through-Silicon-Lifecycle-Monitoring-and-Analytics
Business Development Manager, Hardware Analytics and Test for Europe
Co-Founder and Strategy Consultant
14:40 - 15:00
Agile Analog’s Approach to IP Design, Quality - Why “Silicon Proven” is Not What You Think
While many of todays high end analog IPs are developed to address industry standards, and must be proven according to those standards, most of the baseline analog IP required today needs to deliver design specific functionality, within a power envelop and an area demanded by each, separate SoC. Very little analog IP is used exactly the same way, in the same configuration, more than once. Having to do so usually means you are compromising on what your SoC actually needs. Agile provides just that level of tailored flexibility.
A founder of Agile Analog, Paul has held GM, VP, and Director roles for over 35 years in the Semiconductor, EDA and IP sectors.
Paul has successfully defined and introduced both products and services to some of the world’s biggest electronics companies.
Product Marketing Manager, ASIP Tools
15:00 - 15:20
Softening Hardware: Using Application-Specific Processors to Optimize Modern SoC Designs
System-on-chip (SoC) designers are implementing an increasing amount of functionality in software, to gain flexibility, to mitigate against the uncertainty of evolving application specifications, and to make it possible for a single chip to serve many end products.
Traditionally, designers had to choose between using an existing processor or DSP that is “close enough” to the required functionality, or reverting to the inflexibility of fixed-function hardware. An alternative emerging option is to build an application-specific instruction-set processor (ASIP), whose instruction set and architecture is tailored to the needs of the target application.
In this presentation we will explain how Synopsys’ ASIP Designer enables the efficient design, verification and programming of an ASIP. ASIP Designer’s unique capability to rapidly generate a software development kit (SDK), and the tight integration of the hardware design process into Synopsys’ synthesis and verification flows significantly lower the barrier to adopt ASIPs for new design projects.
Patrick Verbist holds the position of Product Marketing Manager for the Synopsys ASIP Designer tools. Previously he had the role of Business Development Manager and Field Application Engineer for the ASIP Designer tools. Prior to the acquisition by Synopsys in 2014, he was Director of Sales at Target Compiler Technologies. Before Target, Patrick worked for 12 years as Business Development Manager for imec in Belgium and San Jose (US).
He holds a Master’s degree in Electrical Engineering from KU Leuven, Belgium.
Sr. Manager, Applications Engineering DesignWare IPs
15:20 - 15:40
Multi-Die Systems – Challenges and Solutions
Semiconductor chips are becoming more complex, driven by the needs of compute-intensive applications such as High-Performance Computing (HPC) and Artificial intelligence (AI).
At the same time, as Moore’s law wanes, designers are striving to continue advancements for optimal power, performance, area (PPA), and latency.
New innovations in IC design are emerging to address the challenges, and advanced chip packaging technologies are certainly playing a major role.
Multi-die chip designs, consisting of small dies, often on different process nodes and integrated into a single package, are proving to be a worthy option to meet aggressive PPA targets.
A new standard – UCIe, defines die to die electrical interconnect and interface protocol, addressing the need to standardize the Die to Die interface.
Michael Chen is Sr. Manager Applications Engineering at Synopsys Israel, leading technical support for DesignWare interface IPs. He brings more than 25 years of experience in design, architecture and management, covering System, ASIC, FPGA, and IP products for different applications. Michael holds BSEE from Technion, Haifa Israel.