IP & Cores Track
Moderator: Shin (Shimon) Raviv, Director Product Marketing, Weebit Nano
Matti Tommiska
CEO
Xiphera
11:40 - 12:00
Seeding Trust: Hardware-Based Random Number Generation for Cryptographic Security
The quality and security of random number generation are foundational to modern cryptographic applications. In this presentation, Xiphera's CEO Matti Tommiska explores the design, implementation, and deployment of True Random Number Generators (TRNGs) and Pseudorandom Number Generators (PRNGs) on FPGAs.
The presentation covers hardware-based entropy sources, post-processing techniques, and statistical validation methods to ensure cryptographic robustness. It also demonstrates how a hybrid architecture – the combination of a TRNG including an internal entropy source with a high-throughput PRNG – can be efficiently integrated into FPGA logic to deliver scalable and cryptographically secure randomness. Real-world performance benchmarks, design trade-offs, and security implications are discussed, offering insights into deploying FPGA-based random number generation in real-world systems and applications.
BIO:
Matti Tommiska is the CEO and Co-Founder of Xiphera Ltd, a Finnish deep-tech company founded in 2017 to develop and license cryptographic IP cores and security protocols for FPGAs and ASICs. He holds a doctorate in Electrical Engineering (2005) and brings over two decades of experience in semiconductors and secure systems, blending academic depth with hands-on industry expertise. Before founding Xiphera, Matti held senior technical and business roles at Spansion, Altera, and Intel. He now leads Xiphera’s growth in quantum-safe cryptography, secure embedded systems, and trusted digital infrastructure
12:00 - 12:20
Automating the Move to Advanced Technology Nodes
As foundries continue to develop processes and support for FinFet and GAAFet technologies, the global demand for complex SOCs continues to increase, addressing the market demands for ever more capable AI and HPC applications. Design houses are looking for ways to improve their end-product performance, and keep up with evolving design-rules.
In this presentation, Silvaco will present how existing cell libraries can be migrated to new nodes and architectures. These migrations can keep existing placements and routing, update routing only, or create completely new cell layouts from existing CDL files. Silvaco will also show how complementary IP may be included, to optimize the engagement with a given foundry.
BIO:
Andrew has been at Silvaco since 2023, and manages the European business team. Silvaco provides Semiconductor IP, EDA solutions and TCAD design tools to leading Semiconductor Foundries and Design Houses, targeting vertical markets which include AI/HPC, Automotive, Consumer Electronics, Telecomms and more. Prior to Silvaco, Andrew spent 10 years with Mentor Graphics (later Siemens EDA), managing the global Automotive Embedded Software Business Unit. He holds a master’s degree in Electronics and Electrical Engineering from Cambridge University, UK
Andrew Patterson
Business Director
Silvaco EMEA
Ido Gus
Deep Learning Senior Team Leader
Ceva
12:20 - 12:40
NPU IP Hardware Shaped Through Software Insights and Use-Case Analysis
At Ceva, we believe that true innovation in Tiny Machine Learning (TinyML) emerges from synergy of software ingenuity, real-world application insights, and leading-edge processor IP. This presentation will explore the intricate process of integrating these elements to shape the hardware design of our latest NPU IP - the Ceva NeuPro Nano.
Join us, as we examine how software architecture and detailed analysis of use cases were pivotal in guiding the NeuPro Nano NPU architecture design process. This approach ensured a versatile and efficient single-core solution capable of handling control, digital signal processing (DSP), and neural network (NN) inference tasks.
Software plays a crucial role in unlocking the full potential of hardware and adapting to diverse application demands. We will demonstrate how Ceva's TinyML software innovations enhance productivity and support a rapidly growing ecosystem.
Through real-world use cases, we will show how a deep understanding of application requirements informed and refined our hardware design. This ensures that NeuPro Nano is not only technologically advanced but also highly effective in practical scenarios. Harnessing the capabilities of leading neural network inferencing frameworks, such as Tensorflow Lite for Micro Controllers and Micro TVM, has been instrumental in realizing the principles of low code integration and model deployment. The strategic use of advanced frameworks further enhances the adaptability and efficiency of NeuPro Nano.
We will conclude by reviewing the exciting hardware and software extensibility features of NeuPro Nano, which push the boundaries of customizability. This presentation will provide valuable insights into the future of TinyML hardware design, driven by software innovation and real-world application needs.
BIO:
Ido Gus is a Senior Team Leader in Ceva AI Division, where he leads development of advanced Edge AI tooling and applied algorithm research. He brings 18+ years of expertise in software development, algorithm optimization, deep learning, and project management, with a focus on building end-to-end edge AI applications. Ido drives innovation from research to optimized deployment on edge devices, bridging cutting-edge research with real-world impact. He holds a B.Sc. in Information Systems Engineering from Ben Gurion University of the Negev and an MBA from the Hebrew University of Jerusalem.
Lee Harrison
Director Product Marketing Tessent
Siemens EDA
12:40 - 13:00
In-system Test, a Critical Part of Any SLM Solution
A growing number of safety-critical and mission-critical applications require extremely reliable operation. In automotive applications and large-scale data centres, we rely on design-for-test (DFT) not only for manufacturing but throughout the entire silicon lifecycle, but in-system test technology can be coupled with other technologies to provide even more insights into a devices health and reliability.
BIO:
Lee is the Director of Product Marketing Tessent at Siemens Digital Industries Software. He has over 20 years of industry experience with Siemens Tessent test, and safety and security products with a focus on the automotive industry. Lee is working to ensure that current and future test, safety, security and analytics requirements of Siemens’ automotive customers are understood and met.
13:00 - 14:10 : Lunch, Exhibition Visit
Andy Nightingale
VP of Product Management and Marketing
Arteris
14:10 - 14:30
Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplets
Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency. In this talk, Andy will discuss how it can help optimize your NoC designs processes by reducing iterations and bringing unprecedented quality of results.
BIO:
Andy is a seasoned global business leader with a diverse background in engineering and product marketing. He is a Chartered Member of the British Computer Society and the Chartered Institute of Marketing and has over 35 years of experience in the high-tech industry. Throughout his career, Andy has held a range of roles, including engineering and product management positions at Arm, where he spent 23 years. In his current role as VP of product marketing at Arteris, Andy oversees the Magillem System-on-Chip deployment tooling and FlexGen, FlexNoC and Ncore Network-on-Chip products. Prior to this, he led a product marketing team at Arm, specializing in system IP products including network interconnects, memory and interrupt controllers, and system MMUs.
14:30 - 14:50
Next Gen Interfaces & Protocols for Evolving Architectures in AI driven Data Centers
AI performance and bandwidth requirements are driving the next generation interfaces and protocols for new architectures.
Data centers go through changes to support and implement new protocols and network architectures – Scale Up and Scale Out.
New protocols – Ultra Accelerator Link (UALink), Ultra Ethernet, and Ethernet for Scale Up networking (ESUN) are defined to improve network reliability, latency, and speed.
Semiconductors and IPs are crucial part to implement these standards and new interfaces.
Synopsys supports these new developments by offering a wide high speed interface IP portfolio and has recently introduced its Ultra Ethernet and UAL IP solutions.
BIO:
Michael Chen – Director of Applications Engineering, IP Group.
Managing support team in Israel for Interface IPs. Working with key customers on evaluating and selecting IPs for their applications and use cases.
Prior to applications engineering worked as ASIC/SoC design manager, architect and designer at various system and semiconductor companies.
Michael Chen
Applications Engineering, Director IPG, IP Group
Synopsys
Dr. Robert Giterman
Co-Founder and CEO
RAAAM Memory Technologies
14:50 - 15:10
Overcoming Density and Power Barriers in Advanced Node SRAMs
Modern industry growth drivers, such as AI and ML, 5G, and Automotive, require ever-growing amounts of on-chip memory, often dominating the area and power of modern SoCs. SRAM, the predominant on-chip memory technology, has faced scaling challenges due to the sensitivity of its ratioed 6-transistor bitcell, and no longer provides the density requirements in advanced nodes. Gain-Cell RAM (GCRAM) is an emerging memory solution offering up-to 50% size reduction and up-to 10x power reduction vs. SRAM, using only the standard CMOS process flow. This presentation will review available memory options in advanced CMOS nodes and tradeoffs in selecting the appropriate memory technology per application.
BIO:
Robert Giterman is the Co-Founder and CEO of RAAAM Memory Technologies, Ltd, a Bar-Ilan University and EPFL spin-off, which developed the highest-density on-chip memory technology in standard CMOS. Robert holds a PhD in Electrical Engineering from Bar-Ilan University, where he researched alternative memories in advanced CMOS nodes. Prior to establishing RAAAM, he conducted postdoctoral research at EPFL, Lausanne, Switzerland.
Yaacov Belenky
Chief Innovation Officer
FortifyIQ
15:10 - 15:30
Post-quantum Algorithms MS-KEM and MS-DSA Protected Against Physical Attacks, in Hardware and in Software
Post-quantum algorithms ML-KEM and ML-DSA, based on Crystals Kyber and Crystals Dilithium, respectively, have been recently standardized by NIST in FIPS 203 and FIPS 204, and are rapidly adopted worldwide. Unfortunately, these algorithms are extremely prone to side-channel attacks, including side-channel attacks that require only one trace. Masking-based approaches to their security have a significant cost in performance, gate count, and power consumption. In addition, many practical attacks on these masking-based protected implementations have been published in academic papers.
FortifyIQ has developed a unique algorithmic protection against physical attacks for both ML-KEM and ML-DSA, which is not based on masking and has a significantly better PPA than masking-based protections.
It switches the calculations into a large redundant domain, following the same design principles as FortifyIQ’s AES protection schemes, which have passed AVA.VAN.5 evaluation by a leading Common Criteria lab, and are deployed in millions of devices. The protection extends to operations such as composition and decomposition, which are known to be easy targets for side-channel attacks. FortifyIQ offers a combined hardware + firmware solution. For already produced devices or when limitations are preventing the use of this solution, FortifyIQ offers software libraries for both ML-KEM and ML-DSA in which the same algorithmic protection is implemented. Both products use the same unified API.
BIO:
Yaacov was born in the USSR, studied mathematics there, and immigrated to Israel in 1987. Since 1998, he has been working in security, primarily on the hardware level, initially for NDS, (which Cisco later acquired), and later (2017), on Intel’s red team. In 2020, he joined FortifyIQ as Chief Innovation Officer. Since 2013, his focus has been physical attacks and algorithmic protections against them. He has 30 granted patents and 6 academic papers, all security-related.