Physical Design, Power & Signal Integrity
11:40 - 13:00
Track Moderator
Bio
11:40 - 12:00
Will be soon published
Bio
12:00 - 12:20
Avi Braun
Senior Solutions Architect
proteanTecs
Silicon-Aware Power Management for the Agentic AI Era
This session introduces a silicon-aware approach to AI infrastructure power and performance management. While conventional systems rely on workload demand, temperature, power budgets, and static guard bands, they lack direct visibility into each processor’s actual timing margin. As Agentic AI creates increasingly dynamic workloads, this limitation can unnecessarily restrict performance and efficiency.
The proposed approach continuously measures real-time timing margin within the processor. Hardware-generated events reveal how process variation, voltage, temperature, aging, and workload activity affect silicon behavior. This information complements existing DVFS, frequency and voltage management, clock throttling, and cycle-skipping mechanisms, enabling hardware controllers, firmware, software, and schedulers to make more precise decisions.
Attendees will learn how real-time timing-margin visibility can safely reclaim unused voltage guard bands, optimize frequency-voltage operating points, and reduce unnecessary throttling. The result is higher sustained performance, better throughput per watt, and improved reliability throughout the processor’s lifetime, paving the way for infrastructure that is both workload-aware and silicon-aware.
Bio
Avi Braun is a Senior Solutions Architect at proteanTecs, where he helps leading semiconductor and AI infrastructure companies leverage real-time silicon telemetry to optimize performance, power, and reliability. With more than 25 years of experience spanning chip implementation, EDA technologies, and technical leadership, he works at the intersection of silicon, systems, and intelligent infrastructure. Prior to proteanTecs, Avi spent 15 years at Synopsys in senior customer-facing engineering roles and previously held engineering and management positions at Zoran. He studied Electrical and Computer Engineering at the Technion.
12:20 - 12:40
Prof. Alexander Fish
Professor, Vice Dean for Innovation and Industry Relations, Co-Director of ENICS Labs, Faculty of Engineering
Bar-Ilan University
Resurgence of Dynamic Logic and Memories: From Nanoscale CMOS to Cryogenic Computing
Static CMOS logic and SRAM memories have dominated chip design for decades. This talk revisits dynamic circuit operation as a promising alternative to both. In particular, two examples are discussed: Dual Mode Logic (DML) for improved speed and energy efficiency, and Gain-Cell embedded memories offering up to 50% area reduction and 10× lower power than SRAM. In addition, the opportunities offered by cryogenic operation of dynamic circuits for a range of emerging applications are presented.
Bio
Prof. Alexander Fish is the Vice Dean for Innovation and Industry Relations and co-director of the EnICS Impact Center at the Faculty of Engineering, Bar-Ilan University. His research interests include power-reduction methodologies for high-speed digital and mixed-signal VLSI chips, energy-efficient memory arrays, advanced packaging, biomedical circuits and systems, and cryogenic CMOS circuits. In 2021 he co-founded RAAAM Technology, a startup developing area-efficient, low-power embedded memories. He has authored over 200 scientific papers in journals and conferences, filed more than 30 patent applications and published three book chapters and two books as an editor. He serves on numerous IEEE conference committees and as an editor of several journals.
12:40 - 13:00
Moti Zeltser
Siemens EDA
Physical Verification Shift Left With Calibre Platform
Abstract will be soon published