Manufacturing, Packaging & Post-Silicon
14:00 - 15:20
Track Moderator
Bio
14:00 - 14:20
Prof. Leonid Yavits
Prof., EnICS Institute, Engineering faculty
BIU
Advanced 2.5D/3D Packaging in the Age of physical AI
Moore's law scaling is slowing. Transistor density gains come at rising cost and diminishing returns. Advanced 2.5D and 3D packaging has become the primary path to continued system scaling. Chiplet integration, silicon interposers, and hybrid bonding deliver performance gains that monolithic scaling can no longer provide. I argue that packaging capability is also strategic. It underpins national AI independence and supply chain resilience. Physical AI raises the stakes much further. It demands DRAM bandwidth and capacity to maintain and run world models. It requires hybrid package that integrates sensing chiplets alongside compute and memory ones. It imposes strict size, weight, and power budgets. Advanced packaging addresses all those and becomes an enabler of practical physical AI.
Bio
Prof. Leonid Yavits is with EnICS Institute, Engineering faculty, BIU, where he heads the chip design program. His interests include computer architecture in post-Moore’s and post von Neumann era, domain specific (AI) acceleration and advanced packaging. Leonid comes from entrepreneurial background. He was one of the founders of VisionTech, the first Israeli startup acquired by Broadcom in 2001 in a billion-dollar deal.
14:20 - 14:40
Will be soon published
Bio
14:40 - 15:00
Prof. Joseph B. Bernstein
Head of the Microelectronics and VLSI Track of the Electrical and Electronics Engineering Department
Ariel University
Entropic Framework for Post-Silicon Reliability
Modern post-silicon reliability evaluation still depends heavily on empirical acceleration models developed decades ago. As technologies move to GAA devices, wide-bandgap semiconductors, advanced packaging, and increasingly demanding operating conditions, these approaches often provide limited physical insight into how degradation evolves with time and stress.
This talk presents a thermodynamic framework in which reliability degradation is described by power-law kinetics derived from Gibbs free energy. Stress acceleration and the evolution of degradation are represented through measurable entropic parameters, allowing mechanisms such as BTI, HCI, TDDB, electromigration, and fatigue to be described within a common framework while retaining their distinct physical behavior.
Recent results across multiple technologies show that published reliability data can collapse onto surprisingly simple relationships. The approach provides a practical path from accelerated testing toward physics-based lifetime prediction and remaining-useful-life estimation.
Bio
Prof. Joseph B. Bernstein is Professor of Electrical and Electronic Engineering at Ariel University and heads the Ariel Reliable Integrated Electronics Laboratory. He received his Ph.D. in Electrical Engineering from MIT and has worked in semiconductor reliability for more than 35 years in academia and industry.
His research focuses on physics-of-failure, semiconductor and power-device reliability, advanced reliability testing, and lifetime prediction. He has supervised 21 Ph.D. students and approximately 40 M.Sc. students and has published extensively on microelectronics reliability, SiC and GaN devices, reliability-aware circuits, and power-law degradation kinetics. He also advises semiconductor companies on device- and system-level reliability. He is currently applying a new thermodynamic reliability framework to post-silicon evaluation as a practical alternative to conventional industry reliability models.
15:00 - 15:20
Will be soon published