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Front-end Design & Verification

Item List

DV Has a Playbook - Why Doesn’t Formal?

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Roy Frank

Verification Technical Leader, AI-Fabrics

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Guardrailing AI with Formal Verification: Abstract Models as the Anchor of Trust

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Dr. Tobias Ludwig

CEO, LUBIS EDA

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Is RTL Holding Back AI Hardware Generation?

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Oron Port

CEO, DFiant

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Accelerating High-Performance SoC Development with Siemens EDA and Arm: A Software-Aware Verification IP Approach

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Ofer Shragay

Verification Application Engineer, Siemens EDA

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From GVIM/EMACS to Modern IDEs: A Verification Engineer's Journey with DVT

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Netanel Miller

HW Verification Team Leader, Texas Instruments

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Leveraging Formal Verification to Boost Chip Development Process

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Eytan Dreyfus

Formal Verification Director, NVIDIA

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